UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 290 of 523
14.1 How to read this chapter
The I
2
C-bus block is identical for all LPC11U3x/2x/1x parts.
14.2 Basic configuration
The I
2
C-bus interface is configured using the following registers:
1. Pins: The I2C pin functions and the I2C mode are configured in the IOCON register
block (Table 80
and Table 81).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 5 (Table 24
).
3. Reset: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
PRESETCTRL register (Table 8
) is set to 1. This de-asserts the reset signal to the I2C
block.
14.3 Features
• Standard I
2
C-compliant bus interfaces may be configured as Master, Slave, or
Master/Slave.
• Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
• Programmable clock allows adjustment of I
2
C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
• Supports Fast-mode Plus.
• Optional recognition of up to four distinct slave addresses.
• Monitor mode allows observing all I
2
C-bus traffic, regardless of slave address.
• I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus contains a standard I
2
C-compliant bus interface with two pins.
14.4 Applications
Interfaces to external I
2
C standard parts, such as serial RAMs, LCDs, tone generators,
other microcontrollers, etc.
14.5 General description
A typical I
2
C-bus configuration is shown in Figure 40. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I
2
C-bus:
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
Rev. 5.5 — 21 December 2016 User manual