UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 249 of 523
NXP Semiconductors
UM10462
Chapter 12: LPC11U3x/2x/1x USART
12.5.7 USART Line Control Register
The LCR determines the format of the data character that is to be transmitted or received.
Table 237. USART FIFO Control Register Write only (FCR - address 0x4000 8008) bit
description
Bit Symbol Value Description Reset
value
0 FIFOEN FIFO enable 0
0 USART FIFOs are disabled. Must not be used in the application.
1 Active high enable for both USART Rx and TX FIFOs and
FCR[7:1] access. This bit must be set for proper USART
operation. Any transition on this bit will automatically clear the
USART FIFOs.
1RXFIFO
RES
RX FIFO Reset 0
0 No impact on either of USART FIFOs.
1 Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO,
reset the pointer logic. This bit is self-clearing.
2TXFIFO
RES
TX FIFO Reset 0
0 No impact on either of USART FIFOs.
1 Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO,
reset the pointer logic. This bit is self-clearing.
3 - - Reserved 0
5:4 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
7:6 RXTL RX Trigger Level. These two bits determine how many USART
FIFO characters must be received by the FIFO before an
interrupt is activated.
0
0x0 Trigger level 0 (1 character or 0x01).
0x1 Trigger level 1 (4 characters or 0x04).
0x2 Trigger level 2 (8 characters or 0x08).
0x3 Trigger level 3 (14 characters or 0x0E).
31:8 - - Reserved -
Table 238. USART Line Control Register (LCR - address 0x4000 800C) bit description
Bit Symbol Value Description Reset
Value
1:0 WLS Word Length Select 0
0x0 5-bit character length.
0x1 6-bit character length.
0x2 7-bit character length.
0x3 8-bit character length.
2 SBS Stop Bit Select 0
0 1 stop bit.
1 2 stop bits (1.5 if LCR[1:0]=00).
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