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User manual Rev. 5.5 — 21 December 2016 355 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
16.7.1 Interrupt Register
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
Remark: The bit positions for the CAP1 interrupts are different for counter/timer CT32B0
(CAP1 interrupt on bit 6, Table 318
) and counter/timer CT32B1 (CAP1 interrupt on bit 5,
Table 319
).
16.7.2 Timer Control Register
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 318: Interrupt Register (IR, address 0x4001 4000 (CT32B0)) bit description
Bit Symbol Description Reset value
0 MR0INT Interrupt flag for match channel 0. 0
1 MR1INT Interrupt flag for match channel 1. 0
2 MR2INT Interrupt flag for match channel 2. 0
3 MR3INT Interrupt flag for match channel 3. 0
4 CR0INT Interrupt flag for capture channel 0 event. 0
5- Reserved, -
6 CR1INT Interrupt flag for capture channel 1 event. 0
31:7 - Reserved -
Table 319: Interrupt Register (IR, address 0x4001 8000 (CT32B1)) bit description
Bit Symbol Description Reset value
0 MR0INT Interrupt flag for match channel 0. 0
1 MR1INT Interrupt flag for match channel 1. 0
2 MR2INT Interrupt flag for match channel 2. 0
3 MR3INT Interrupt flag for match channel 3. 0
4 CR0INT Interrupt flag for capture channel 0 event. 0
5 CR1INT Interrupt flag for capture channel 1 event. 0
31:6 - Reserved -
Table 320: Timer Control Register (TCR, address 0x4001 4004 (CT32B0) and 0x4001 8004
(CT32B1)) bit description
Bit Symbol Value Description Reset
value
0 CEN Counter enable. 0
0 The counters are disabled.
1 The Timer Counter and Prescale Counter are enabled
for counting.