UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 224 of 523
NXP Semiconductors
UM10462
Chapter 11: LPC11U3x/2x/1x USB2.0 device controller
To use the SoftConnect feature, the CONNECT signal should control an external switch
that connects the 1.5 kOhm resistor between USB_DP and V
DD
(+3.3 V). Software can
then control the CONNECT signal by writing to the DCON bit in the DEVCMDSTAT
register.
11.4.4 Interrupts
The USB controller has two interrupt lines USB_Int_Req_IRQ and USB_Int_Req_FIQ.
Software can program the corresponding bit in the USB interrupt routing register to route
the interrupt condition to one of these entries in the NVIC table Table 59
. An interrupt is
generated by the hardware if both the interrupt status bit and the corresponding interrupt
enable bit are set. The interrupt status bit is set by hardware if the interrupt condition
occurs (irrespective of the interrupt enable bit setting).
11.4.5 Suspend and resume
The USB protocol insists on power management by the USB device. This becomes even
more important if the device draws power from the bus (bus-powered device). The
following constraints should be met by the bus-powered device.
• A device in the non-configured state should draw a maximum of 100mA from the
USB bus.
• A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
• A suspended device should draw a maximum of 500 A.
A device will go into the L2 suspend state if there is no activity on the USB bus for more
than 3 ms. A suspended device wakes up, if there is transmission from the host
(host-initiated wake up). The USB controller on the LPC11U3x/2x/1x also supports
software initiated remote wake-up. To initiate remote wake-up, software on the device
must enable all clocks and clear the suspend bit. This will cause the hardware to generate
a remote wake-up signal upstream.
The USB controller on the LPC11U3x/2x/1x supports Link Power Management (LPM).
Link Power Management defines an additional link power management state L1 that
supplements the existing L2 state by utilizing most of the existing suspend/resume
infrastructure but provides much faster transitional latencies between L1 and L0 (On).
The assertion of USB suspend signal indicates that there was no activity on the USB bus
for the last 3 ms. At this time an interrupt is sent to the processor on which the software
can start preparing the device for suspend.
If there is no activity for the next 2 ms, the USB need_clock signal will go low. This
indicates that the USB main clock can be switched off.
When activity is detected on the USB bus, the USB suspend signal is deactivated and
USB need_clock signal is activated. This process is fully combinatorial and hence no USB
main clock is required to activate the US B need_clock signal.
11.4.6 Frame toggle output
The USB_FTOGGLE output pin reflects the 1 kHz clock derived from the incoming Start of
Frame tokens sent by the USB host.
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