UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 129 of 523
NXP Semiconductors
UM10462
Chapter 8: LPC11U3x/2x/1x Pin configuration
8.2 Pin configuration
Fig 15. Pin configuration (HVQFN33)
002aaf888_1
Transparent top view
PIO0_8/MISO0/CT16B0_MAT0
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1
XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0
RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
USB_DM
USB_DP
PIO0_6/USB_CONNECT/SCK0
PIO0_7/CTS
PIO0_19/TXD/CT32B0_MAT1
PIO0_18/RXD/CT32B0_MAT0
PIO0_17/RTS/CT32B0_CAP0/SCLK
V
DD
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_23/AD7
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
33 V
SS
LPC11U1x
LPC11U2x
LPC11U3x
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