UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 75 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.5 Interrupt Active Bit Register 0
The IABR0 register is a read-only register that allows reading the active state of the
peripheral interrupts. Use this register to determine which peripherals are asserting an
interrupt to the NVIC and may also be pending if there are enabled.
The bit description is as follows for all bits in this register:
Write — n/a.
Read — 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
11 - Reserved. 0
12 - Reserved. 0
13 - Reserved. 0
14 ICP_SSP1 Interrupt pending clear. 0
15 ICP_I2C0 Interrupt pending clear. 0
16 ICP_CT16B0 Interrupt pending clear. 0
17 ICP_CT16B1 Interrupt pending clear. 0
18 ICP_CT32B0 Interrupt pending clear. 0
19 ICP_CT32B1 Interrupt pending clear. 0
20 ICP_SSP0 Interrupt pending clear. 0
21 ICP_USART0 Interrupt pending clear. 0
22 ICP_USB_IRQ Interrupt pending clear. 0
23 ICP_USB_FIQ Interrupt pending clear. 0
24 ICP_ADC Interrupt pending clear. 0
25 ICP_WWDT Interrupt pending clear. 0
26 ICP_BOD Interrupt pending clear. 0
27 ICP_FLASH Interrupt pending clear. 0
28 - Reserved. 0
29 - Reserved. 0
30 ICP_USB_WAKEKUP Interrupt pending clear. 0
31 ICP_IOH Interrupt pending clear. 0
Table 64. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit
description
…continued
Bit Symbol Function Reset value
Table 65. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description
Bit Symbol Function Reset value
0 IAB_PININT0 Interrupt active state. 0
1 IAB_PININT1 Interrupt active state. 0
2 IAB_PININT2 Interrupt active state. 0
3 IAB_PININT3 Interrupt active state. 0
4 IAB_PININT4 Interrupt active state. 0
5 IAB_PININT5 Interrupt active state. 0
6 IAB_PININT6 Interrupt active state. 0
7 IAB_PININT7 Interrupt active state. 0
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