NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 72 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.2 Interrupt clear enable register 0
The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled
state of those interrupts. Enable interrupts through the ISER0 registers (Section 6.5.1
).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 disables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
22 ISE_USB_IRQ Interrupt enable. 0
23 ISE_USB_FIQ Interrupt enable. 0
24 ISE_ADC Interrupt enable. 0
25 ISE_WWDT Interrupt enable. 0
26 ISE_BOD Interrupt enable. 0
27 ISE_FLASH Interrupt enable. 0
28 - Reserved. 0
29 - Reserved. 0
30 ISE_USB_WAKEKUP Interrupt enable. 0
31 ISE_IOH Interrupt enable. 0
Table 61. Interrupt Set Enable Register 0 register (ISER0, address 0xE000 E100) bit
description
…continued
Bit Symbol Description Reset value
Table 62. Interrupt clear enable register 0 (ICER0, address 0xE000 E180)
Bit Symbol Description Reset value
0 ICE_PININT0 Interrupt disable. 0
1 ICE_PININT1 Interrupt disable. 0
2 ICE_PININT2 Interrupt disable. 0
3 ICE_PININT3 Interrupt disable. 0
4 ICE_PININT4 Interrupt disable. 0
5 ICE_PININT5 Interrupt disable. 0
6 ICE_PININT6 Interrupt disable. 0
7 ICE_PININT7 Interrupt disable. 0
8 ICE_GINT0 Interrupt disable. 0
9 ICE_GINT1 Interrupt disable. 0
10 - Reserved. 0
11 - Reserved. 0
12 - Reserved. 0
13 - Reserved. 0
14 ICE_SSP1 Interrupt disable. 0
15 ICE_I2C0 Interrupt disable. 0
16 ICE_CT16B0 Interrupt disable. 0
17 ICE_CT16B1 Interrupt disable. 0
18 ICE_CT32B0 Interrupt disable. 0
19 ICE_CT32B1 Interrupt disable. 0

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English