UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 76 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.6 Interrupt Priority Register 0
The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.
8 IAB_GINT0 Interrupt active state. 0
9 IAB_GINT1 Interrupt active state. 0
10 - Reserved. 0
11 - Reserved. 0
12 - Reserved. 0
13 - Reserved. 0
14 IAB_SSP1 Interrupt active state. 0
15 IAB_I2C0 Interrupt active state. 0
16 IAB_CT16B0 Interrupt active state. 0
17 IAB_CT16B1 Interrupt active state. 0
18 IAB_CT32B0 Interrupt active state. 0
19 IAB_CT32B1 Interrupt active state. 0
20 IAB_SSP0 Interrupt active state. 0
21 IAB_USART0 Interrupt active state. 0
22 IAB_USB_IRQ Interrupt active state. 0
23 IAB_USB_FIQ Interrupt active state. 0
24 IAB_ADC Interrupt active state. 0
25 IAB_WWDT Interrupt active state. 0
26 IAB_BOD Interrupt active state. 0
27 IAB_FLASH Interrupt active state. 0
28 - Reserved. 0
29 - Reserved. 0
30 IAB_USB_WAKEKUP Interrupt active state. 0
31 IAP_IOH Interrupt active state. 0
Table 65. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description
Bit Symbol Function Reset value
Table 66. Interrupt Priority Register 0 (IPR0, address 0xE000 E400) bit description
Bit Symbol Description Reset value
5:0 - These bits ignore writes, and read as 0. 0
7:6 IP_PIN_INT0 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
13:8 - These bits ignore writes, and read as 0. 0
15:14 IP_PIN_INT1 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
21:16 - These bits ignore writes, and read as 0. 0
23:22 IP_PIN_INT2 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
29:24 - These bits ignore writes, and read as 0. 0
31:30 IP_PIN_INT3 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
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