UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 349 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
15.8 Example timer operation
Figure 57 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 58
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
15.9 Architecture
The block diagram for counter/timer0 and counter/timer1 is shown in Figure 59.
Fig 57. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
222200001111
45 6 0 1
Fig 58. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK
prescale counter
interrupt
timer counter
TCR[0]
(counter enable)
220 01
45 6
1 0
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