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NXP Semiconductors LPC11U3x User Manual

NXP Semiconductors LPC11U3x
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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 158 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
9.5.1.4 Pin interrupt level (rising edge interrupt) clear register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit
in the CIENR register clears the corresponding bit in the IENR register depending on the
pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
cleared.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared.
9.5.1.5 Pin interrupt active level (falling edge) interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit
in the IENF register enables the falling edge interrupt or the configures the level sensitivity
depending on the pin interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is
enabled.
• If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level
interrupt (HIGH or LOW) is configured.
Table 143. Pin interrupt level (rising edge) interrupt set register (SIENR, address 0x4004
C008) bit description
Bit Symbol Description Reset
value
Access
7:0 SETENRL Ones written to this address set bits in the IENR, thus
enabling interrupts. Bit n sets bit n in the IENR register.
0 = No operation.
1 = Enable rising edge or level interrupt.
NA WO
31:8 - Reserved. - -
Table 144. Pin interrupt level (rising edge interrupt) clear register (CIENR, address 0x4004
C00C) bit description
Bit Symbol Description Reset
value
Access
7:0 CENRL Ones written to this address clear bits in the IENR, thus
disabling the interrupts. Bit n clears bit n in the IENR
register.
0 = No operation.
1 = Disable rising edge or level interrupt.
NA WO
31:8 - Reserved. - -

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NXP Semiconductors LPC11U3x Specifications

General IconGeneral
BrandNXP Semiconductors
ModelLPC11U3x
CategoryMicrocontrollers
LanguageEnglish

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