UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 37 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in
this register, can wake-up the chip from Sleep, Deep-sleep, and Power-down modes. See
Section 3.9
.
3.5.31 System tick counter calibration register
This register determines the value of the SYST_CALIB register (see Table 349).
3.5.32 IRQ latency register
The IRQLATENCY register is an eight-bit register which specifies the minimum number of
cycles (0-255) permitted for the system to respond to an interrupt request. The intent of
this register is to allow the user to select a trade-off between interrupt response time and
determinism.
Table 36. BOD control register (BODCTRL, address 0x4004 8150) bit description
Bit Symbol Value Description Reset
value
1:0 BODRSTLEV BOD reset level 0
0x0 Level 0: The reset assertion threshold voltage is 1.46 V; the
reset de-assertion threshold voltage is 1.63 V.
0x1 Level 1: The reset assertion threshold voltage is 2.06 V; the
reset de-assertion threshold voltage is 2.15 V.
0x2 Level 2: The reset assertion threshold voltage is 2.35 V; the
reset de-assertion threshold voltage is 2.43 V.
0x3 Level 3: The reset assertion threshold voltage is 2.63 V; the
reset de-assertion threshold voltage is 2.71 V.
3:2 BODINTVAL BOD interrupt level 0
0x0 Level 0: Reserved.
0x1 Level 1:The interrupt assertion threshold voltage is 2.22 V;
the interrupt de-assertion threshold voltage is 2.35 V.
0x2 Level 2: The interrupt assertion threshold voltage is 2.52 V;
the interrupt de-assertion threshold voltage is 2.66 V.
0x3 Level 3: The interrupt assertion threshold voltage is 2.80 V;
the interrupt de-assertion threshold voltage is 2.90 V.
4 BODRSTENA BOD reset enable 0
0 Disable reset function.
1 Enable reset function.
31:5 - - Reserved 0x00
Table 37. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit
description
Bit Symbol Description Reset
value
25:0 CAL System tick timer calibration value 0
31:26 - Reserved -
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