UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 43 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.41 Power configuration register
The PDRUNCFG register controls the power to the various analog blocks. This register
can be written to at any time while the chip is running, and a write will take effect
immediately with the exception of the power-down signal to the IRC.
To avoid glitches when powering down the IRC, the IRC clock is automatically switched off
at a clean point. Therefore, for the IRC a delay is possible before the power-down state
takes effect.
9 - 0 Reserved. 0
10 USBPAD_PD USB transceiver wake-up configuration 1
0 USB transceiver powered
1 USB transceiver powered down
11 - Reserved. Always write this bit as 1. 1
12 - Reserved. Always write this bit as 0. 0
15:13 - Reserved. Always write these bits as 111. 111
31:16 - - Reserved -
Table 46. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 47. Power configuration register (PDRUNCFG, address 0x4004 8238) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output power-down 0
0 Powered
1 Powered down
1 IRC_PD IRC oscillator power-down 0
0 Powered
1 Powered down
2 FLASH_PD Flash power-down 0
0 Powered
1 Powered down
3 BOD_PD BOD power-down 0
0 Powered
1 Powered down
4 ADC_PD ADC power-down 1
0 Powered
1 Powered down
5 SYSOSC_PD Crystal oscillator power-down 0
0 Powered
1 Powered down
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