UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 162 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
9.5.2.3 GPIO grouped interrupt port enable registers
The grouped interrupt port enable registers enable the pins which contribute to the
grouped interrupt. Each port is associated with its own port enable register, and the values
of both registers together determine which pins contribute to the grouped interrupt.
Table 152. GPIO grouped interrupt port 0 polarity registers (PORT_POL0, addresses 0x4005
C020 (GROUP0 INT) and 0x4006 0020 (GROUP1 INT)) bit description
Bit Symbol Description Reset
value
Access
31:0 POL0 Configure pin polarity of port 0 pins for group interrupt. Bit n
corresponds to pin P0_n of port 0.
0 = the pin is active LOW. If the level on this pin is LOW, the
pin contributes to the group interrupt.
1 = the pin is active HIGH. If the level on this pin is HIGH, the
pin contributes to the group interrupt.
1-
Table 153. GPIO grouped interrupt port 1 polarity registers (PORT_POL1, addresses 0x4005
C024 (GROUP0 INT) and 0x4006 0024 (GROUP1 INT)) bit description
Bit Symbol Description Reset
value
Access
31:0 POL1 Configure pin polarity of port 1 pins for group interrupt. Bit n
corresponds to pin P1_n of port 1.
0 = the pin is active LOW. If the level on this pin is LOW, the
pin contributes to the group interrupt.
1 = the pin is active HIGH. If the level on this pin is HIGH, the
pin contributes to the group interrupt.
1-
Table 154. GPIO grouped interrupt port 0 enable registers (PORT_ENA0, addresses 0x4005
C040 (GROUP0 INT) and 0x4006 0040 (GROUP1 INT)) bit description
Bit Symbol Description Reset
value
Access
31:0 ENA0 Enable port 0 pin for group interrupt. Bit n corresponds to pin
P0_n of port 0.
0 = the port 0 pin is disabled and does not contribute to the
grouped interrupt.
1 = the port 0 pin is enabled and contributes to the grouped
interrupt.
0-
Table 155. GPIO grouped interrupt port 1 enable registers (PORT_ENA1, addresses 0x4005
C044 (GROUP0 INT) and 0x4006 0044 (GROUP1 INT)) bit description
Bit Symbol Description Reset
value
Access
31:0 ENA1 Enable port 1 pin for group interrupt. Bit n corresponds to pin
P1_n of port 0.
0 = the port 1 pin is disabled and does not contribute to the
grouped interrupt.
1 = the port 1 pin is enabled and contributes to the grouped
interrupt.
0-
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