UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 366 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
Note: When the match outputs are selected to perform as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to
zero except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to one to enable the timer reset when the timer value matches the value of the
corresponding match register.
16.8 Example timer operation
Figure 61 shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 62
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
Fig 60. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR2) and
MAT2:0 enabled as PWM outputs by the PWMC register.
100
(counter is reset)
04165
PWM0/MAT0
PWM1/MAT1
PWM2/MAT2 MR2 = 100
MR1 = 41
MR0 = 65
Fig 61. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
222200001111
45 6 0 1
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