UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 6 of 523
1.1 Introduction
The LPC11U3x/2x/1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory5 addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC11U3x/2x/1x operate at CPU frequencies of up to 50 MHz. Equipped with a
highly flexible and configurable full-speed USB 2.0 device controller, the LPC11U3x/2x/1x
bring unparalleled design flexibility and seamless integration to today's demanding
connectivity solutions.
The peripheral complement of the LPC11U3x/2x/1x includes up to 32 kB of flash memory,
up to 8 kB of SRAM data memory, one Fast-mode Plus I
2
C-bus interface, one
RS-485/EIA-485 USART with support for synchronous mode and smart card interface,
two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54
general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O handler applications are available on http://www.LPCware.com
.
See Section 25.2 “References”
for additional documentation related to the LPC11Uxx
parts.
1.2 Features
• System:
– ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
– ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
– Non Maskable Interrupt (NMI) input selectable from several input sources.
– System tick timer.
• Memory:
– Up to 32 kB on-chip flash program memory.
– LPC11U3x only: Up to 128 kB on-chip flash program memory with sector (4 kB)
and page erase (256 byte) access.
– In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
– Total SRAM
LPC11U1x: up to 6 kB (4 kB main SRAM and 2 kB USB SRAM).
LPC11U2x: up to 10 kB (8 kB main SRAM and 2 kB USB SRAM).
UM10462
Chapter 1: LPC11U3x/2x/1x Introductory information
Rev. 5.5 — 21 December 2016 User manual
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