UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 5 of 523
NXP Semiconductors
UM10462
Chapter :
• Flash page erase command added for LPC11U3x parts in Chapter 20.
• FREQSEL bit values updated in Table 14 “Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit description”.
• SRAM use by bootloader specified in Section 20.2.
• Description of interrupt use with IAP calls updated (see Section 20.8.7).
• Description of ISP Go command updated (only Thumb mode allowed) in Table 357.
• Update EEPROM write command. The top 64 bytes are reserved for the 4 kB EEPROM
only (see Section 20.14.11).
• Description of the BYPASS bit corrected in Table 13 “System oscillator control register
(SYSOSCCTRL, address 0x4004 8020) bit description”.
• Description of USB CDC device class updated in Table 186 “USBD_CDC_API class
structure” and Table 187 “USBD_CDC_INIT_PARAM class structure”.
• IRC suitable for USB clocking in low-speed mode (see Section 11.4.7 and
Section 3.5.12).
• Figure 8 “Start-up timing” updated (RESET changed to internal reset).
• Figure 66 corrected.
2.1 20120113 Modifications:
• Description of PIOPOR1CAP register updated (see Table 34).
• LPM register added (Table 201).
2 20111214 LPC11U3x/2x/1x User manual
Modifications:
• Parts LPC11U2x added.
• Chapter 22 added.
• Part LPC11U14FHI33/201 added.
Modifications:
• Parts LPC11U2x added.
• Chapter 22 added.
• Part LPC11U14FHI33/201 added.
• Bit 10 (TD) changed to reserved for PIO0_4 and PIO0_5 registers (Table 65, Table 66).
1 20110414 Initial version
Revision history …continued
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