UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 79 of 523
NXP Semiconductors
UM10462
Chapter 6: LPC11U3x/2x/1x NVIC
6.5.13 Interrupt Priority Register 7
The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 4 priorities, where 0 is the highest priority.
Table 73. Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description
Bit Symbol Description Reset value
5:0 - These bits ignore writes, and read as 0. 0
7:6 - Reserved. 0
13:8 - These bits ignore writes, and read as 0. 0
15:14 - Reserved. 0
21:16 - These bits ignore writes, and read as 0. 0
23:22 IP_USB_WAKEUP Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
29:24 - These bits ignore writes, and read as 0. 0
31:30 IP_IOH Interrupt Priority. 0 = highest priority. 3 = lowest priority. 0
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