UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 373 of 523
NXP Semiconductors
UM10462
Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)
17.8 Register description
The Watchdog Timer contains the registers shown in Table 336.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
17.8.1 Watchdog mode register
The WDMOD register controls the operation of the Watchdog. Note that a watchdog feed
must be performed before any changes to the WDMOD register take effect.
Table 336. Register overview: Watchdog timer (base address 0x4000 4000)
Name Access Address
offset
Description Reset
Value
[1]
Reference
MOD R/W 0x000 Watchdog mode register. This
register contains the basic mode and
status of the Watchdog Timer.
0 Table 337
TC R/W 0x004 Watchdog timer constant register.
This 24-bit register determines the
time-out value.
0xFF Table 339
FEED WO 0x008 Watchdog feed sequence register.
Writing 0xAA followed by 0x55 to this
register reloads the Watchdog timer
with the value contained in WDTC.
NA Table 340
TV RO 0x00C Watchdog timer value register. This
24-bit register reads out the current
value of the Watchdog timer.
0xFF Table 341
CLKSEL R/W 0x010 Watchdog clock select register. 0 Table 342
WARNINT R/W 0x014 Watchdog Warning Interrupt compare
value.
0 Table 343
WINDOW R/W 0x018 Watchdog Window compare value. 0xFF FFFF Table 344
Table 337. Watchdog mode register (MOD - 0x4000 4000) bit description
Bit Symbol Value Description Reset
value
0 WDEN Watchdog enable bit. Once this bit has been written with
a 1, it cannot be rewritten with a 0.
0
0 The watchdog timer is stopped.
1 The watchdog timer is running.
1 WDRESET Watchdog reset enable bit. Once this bit has been
written with a 1 it cannot be rewritten with a 0.
0
0 A watchdog timeout will not cause a chip reset.
1 A watchdog timeout will cause a chip reset.
2 WDTOF Watchdog time-out flag. Set when the watchdog timer
times out, by a feed error, or by events associated with
WDPROTECT. Cleared by software. Causes a chip
reset if WDRESET = 1.
0 (only
after
external
reset)
3 WDINT Warning interrupt flag. Set when the timer reaches the
value in WDWARNINT. Cleared by software.
0
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