UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 374 of 523
NXP Semiconductors
UM10462
Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)
Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by
software. Both flags are cleared by an external reset or a Watchdog timer reset.
WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed
error occurs, or when PROTECT =1 and an attempt is made to write to the TC register.
This flag is cleared by software writing a 0 to this bit.
WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 1 to this bit.
In all power modes except Deep power-down mode, a Watchdog reset or interrupt can
occur when the watchdog is running and has an operating clock source. The watchdog
oscillator or the IRC can be selected to keep running in Sleep and Deep-sleep modes. In
Power-down mode, only the watchdog oscillator is allowed. If a watchdog interrupt occurs
in Sleep, Deep-sleep mode, or Power-down mode and the WWDT interrupt is enabled in
the NVIC, the device will wake up. Note that in Deep-sleep and Power-down modes, the
WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC.
4 WDPROTECT Watchdog update mode. This bit can be set once by
software and is only cleared by a reset.
0
0 The watchdog time-out value (TC) can be changed at
any time.
1 The watchdog time-out value (TC) can be changed only
after the counter is below the value of WDWARNINT
and WDWINDOW.
5 LOCK A 1 in this bit prevents disabling or powering down the
clock source selected by bit 0 of the WDCLKSRC
register and also prevents switching to a clock source
that is disabled or powered down. This bit can be set
once by software and is only cleared by any reset.
Remark: If this bit is one and the WWDT clock source is
the IRC when Deep-sleep or Power-down modes are
entered, the IRC remains running thereby increasing
power consumption in Deep-sleep mode and potentially
preventing the part from entering Power-down mode
correctly (see Section 17.7
).
0
31:6 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 337. Watchdog mode register (MOD - 0x4000 4000) bit description
Bit Symbol Value Description Reset
value
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