UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 337 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
15.7.1 Interrupt Register
The Interrupt Register consists of four bits for the match interrupts and two bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
Remark: The bit positions for the CAP1 interrupts are different for counter/timer CT16B0
(CAP1 interrupt on bit 6, Table 297
) and counter/timer CT16B1 (CAP1 interrupt on bit 5,
Table 298
).
15.7.2 Timer Control Register
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 297. Interrupt Register (IR, address 0x4000 C000 (CT16B0)) bit description
Bit Symbol Description Reset value
0 MR0INT Interrupt flag for match channel 0. 0
1 MR1INT Interrupt flag for match channel 1. 0
2 MR2INT Interrupt flag for match channel 2. 0
3 MR3INT Interrupt flag for match channel 3. 0
4 CR0INT Interrupt flag for capture channel 0 event. 0
5 - Reserved. -
6 CR1INT Interrupt flag for capture channel 1 event. 0
31:7 - Reserved -
Table 298. Interrupt Register (IR, address 0x4001 0000 (CT16B1)) bit description
Bit Symbol Description Reset value
0 MR0INT Interrupt flag for match channel 0. 0
1 MR1INT Interrupt flag for match channel 1. 0
2 MR2INT Interrupt flag for match channel 2. 0
3 MR3INT Interrupt flag for match channel 3. 0
4 CR0INT Interrupt flag for capture channel 0 event. 0
5 CR1INT Interrupt flag for capture channel 1 event. 0
6 - Reserved. -
31:7 - Reserved -
Table 299. Timer Control Register (TCR, address 0x4000 C004 (CT16B0) and 0x4001 0004
(CT16B1)) bit description
Bit Symbol Value Description Reset
value
0 CEN Counter enable. 0
0 The counters are disabled.
1 The Timer Counter and Prescale Counter are enabled for
counting.
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