UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 295 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
1. The address in the Slave Address Register has been received.
2. The General Call address has been received while the General Call bit (GC) in the
ADR register is set.
3. A data byte has been received while the I
2
C is in the master receiver mode.
4. A data byte has been received while the I
2
C is in the addressed slave receiver mode
The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is
0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
1. A data byte has been received while the I
2
C is in the master receiver mode.
2. A data byte has been received while the I
2
C is in the addressed slave receiver mode.
14.7.2 I
2
C Status register (STAT)
Each I
2
C Status register reflects the condition of the corresponding I
2
C interface. The I
2
C
Status register is Read-Only.
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
2
C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 287
to Table 292.
14.7.3 I
2
C Data register (DAT)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in DAT register remains stable as long as the SI bit is set. Data in DAT
register is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7),
and after a byte has been received, the first bit of received data is located at the MSB of
the DAT register.
Table 272. I
2
C Status register (STAT - 0x4000 0004) bit description
Bit Symbol Description Reset value
2:0 - These bits are unused and are always 0. 0
7:3 Status These bits give the actual status information about the I
2
C
interface.
0x1F
31:8 - Reserved. The value read from a reserved bit is not defined. -
Table 273. I
2
C Data register (DAT - 0x4000 0008) bit description
Bit Symbol Description Reset value
7:0 Data This register holds data values that have been received or are to
be transmitted.
0
31:8 - Reserved. The value read from a reserved bit is not defined. -
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