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NXP Semiconductors LPC11U3x

NXP Semiconductors LPC11U3x
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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 357 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
16.7.6 Match Control Register
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in Table 324
.
Table 324: Match Control Register (MCR, address 0x4001 4014 (CT32B0) and 0x4001 8014 (CT32B1)) bit description
Bit Symbol Value Description Reset
value
0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0
1 Enabled
0 Disabled
1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0
1 Enabled
0 Disabled
2 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
0
1 Enabled
0 Disabled
3 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0
1 Enabled
0 Disabled
4 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0
1 Enabled
0 Disabled
5 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
0
1 Enabled
0 Disabled
6 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0
1 Enabled
0 Disabled
7 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0
1 Enabled
0 Disabled
8 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
0
1 Enabled
0 Disabled
9 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0
1 Enabled
0 Disabled
10 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0
1 Enabled
0 Disabled

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