NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 157 of 523
NXP Semiconductors
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
9.5.1 GPIO pin interrupts register description
9.5.1.1 Pin interrupt mode register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit
in the ISEL register determines whether the interrupt is edge or level sensitive.
9.5.1.2 Pin interrupt level (rising edge) interrupt enable register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit
in the IENR register enables the interrupt depending on the pin interrupt mode configured
in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
enabled.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.
The IENF register configures the active level (HIGH or LOW) for this interrupt.
9.5.1.3 Pin interrupt level (rising edge) interrupt set register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 40), one bit
in the SIENR register sets the corresponding bit in the IENR register depending on the pin
interrupt mode configured in the ISEL register:
• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
set.
• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set.
Table 141. Pin interrupt mode register (ISEL, address 0x4004 C000) bit description
Bit Symbol Description Reset
value
Access
7:0 PMODE Selects the interrupt mode for each pin interrupt. Bit n
configures the pin interrupt selected in PINTSELn.
0 = Edge sensitive
1 = Level sensitive
0R/W
31:8 - Reserved. - -
Table 142. Pin interrupt level (rising edge) interrupt enable register (IENR, address 0x4004
C004) bit description
Bit Symbol Description Reset
value
Access
7:0 ENRL Enables the rising edge or level interrupt for each pin
interrupt. Bit n configures the pin interrupt selected in
PINTSELn.
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt.
0R/W
31:8 - Reserved. - -

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English