UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 19 of 523
3.1 How to read this chapter
The system control block is identical for all LPC11U3x/2x/1x parts.
The following register bit is available on LPC11U3x/501 and LPC11U37H only and is
reserved otherwise: SYSAHBCLKCTRL register bit RAM1 (bit 26) (Table 24
).
Remark: For part LPC11U37H, enable the SRAM1 clock in the SYSAHBCLKCTRL
(Table 24
) register for running the I/O Handler software library code.
The DEVICE_ID register contains the device id numbers for the LPC11U1x and
LPC11U2x parts. For LPC11U3x parts, see the ISP/IAP Read Part Id command
(Table 376
).
3.2 Introduction
The system configuration block controls oscillators, some aspects of the power
management, and the clock generation of the LPC11U3x/2x/1x. Also included in this block
is a register for remapping flash, SRAM, and ROM memory areas.
3.3 Pin description
Table 4 shows pins that are associated with system control block functions.
3.4 Clocking and power control
See Figure 7 for an overview of the LPC11U3x/2x/1x Clock Generation Unit (CGU).
The LPC11U3x/2x/1x include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC11U3x/2x/1x will operate from the Internal RC oscillator until
switched by software. This allows systems to operate without an external crystal and the
bootloader code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. USART and SSP have individual clock dividers to derive peripheral clocks
from the main clock.
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
Rev. 5.5 — 21 December 2016 User manual
Table 4. Pin summary
Pin name Pin
direction
Pin description
CLKOUT O Clockout pin
PIO0 and PIO1 pins I Eight pins can be selected as external interrupt
pins from all available GPIO pins (see Table 40
).
To Next Page
Loading...
Need help?
General
