UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 275 of 523
13.1 How to read this chapter
Two SSP/SPI interfaces are available on all LPC11U3x/2x/1x parts.
13.2 Basic configuration
The SSP0/1 are configured using the following registers:
1. Pins: The SSP/SPI pins must be configured in the IOCON register block.
2. Power: In the SYSAHBCLKCTRL register, set bit 11 for SSP0 and bit 18 for SSP1
(Table 24
).
3. Peripheral clock: Enable the SSP0/SSP1 peripheral clocks by writing to the
SSP0/1CLKDIV registers (Table 25
/Table 27).
4. Reset: Before accessing the SSP/SPI block, ensure that the SSP0/1_RST_N bits (bit
0 and bit 2) in the PRESETCTRL register (Table 8
) are set to 1. This de-asserts the
reset signal to the SSP/SPI block.
13.3 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
• Synchronous Serial Communication.
• Supports master or slave operation.
• Eight-frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
13.4 General description
The SSP/SPI is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
Rev. 5.5 — 21 December 2016 User manual
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