UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 369 of 523
17.1 How to read this chapter
The WWDT is identical on all LPC11U3x/2x/1x parts.
17.2 Basic configuration
The WWDT is configured through the following registers:
• Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL
register, set bit 15 in Table 24
.
• Enable the WWDT clock source (the watchdog oscillator or the IRC) in the
PDRUNCFG register (Table 47
).
• For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in
the STARTERP1 register (Table 44
).
17.3 Features
• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Programmable 24-bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (T
WDCLK
256 4) to over 67
million watchdog clocks (T
WDCLK
2
24
4) in increments of 4 watchdog clocks.
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
• Incorrect feed sequence causes immediate watchdog event if enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
• Flag to indicate Watchdog reset.
• The Watchdog clock (WDCLK) source can be selected as the Internal High frequency
oscillator (IRC) or the WatchDog oscillator.
• The Watchdog timer can be configured to run in Deep-sleep or Power-down mode
when using the watchdog oscillator as the clock source.
• Debug mode.
UM10462
Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer
(WWDT)
Rev. 5.5 — 21 December 2016 User manual
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