UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 42 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
3.5.40 Wake-up configuration register
This register controls the power configuration of the device when waking up from
Deep-sleep or Power-down mode.
6 WDTOSC_PD Watchdog oscillator power-down control for Deep-sleep
and Power-down mode
1
0 Powered
1 Powered down
31:7 - - Reserved -
Table 45. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 46. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output wake-up configuration 0
0 Powered
1 Powered down
1 IRC_PD IRC oscillator power-down wake-up configuration 0
0 Powered
1 Powered down
2 FLASH_PD Flash wake-up configuration 0
0 Powered
1 Powered down
3 BOD_PD BOD wake-up configuration 0
0 Powered
1 Powered down
4 ADC_PD ADC wake-up configuration 1
0 Powered
1 Powered down
5 SYSOSC_PD Crystal oscillator wake-up configuration 1
0 Powered
1 Powered down
6 WDTOSC_PD Watchdog oscillator wake-up configuration 1
0 Powered
1 Powered down
7 SYSPLL_PD System PLL wake-up configuration 1
0 Powered
1 Powered down
8 USBPLL_PD USB PLL wake-up configuration 1
0 Powered
1 Powered down
To Next Page
Loading...
Need help?
General
