UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 255 of 523
NXP Semiconductors
UM10462
Chapter 12: LPC11U3x/2x/1x USART
12.5.10 USART Modem Status Register
The MSR is a read-only register that provides status information on USART input signals.
Bit 0 is cleared when (after) this register is read.
12.5.11 USART Scratch Pad Register
The SCR has no effect on the USART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the SCR has occurred.
Table 242: USART Modem Status Register (MSR - address 0x4000 8018) bit description
Bit Symbol Value Description Reset
value
0 DCTS Delta CTS.
Set upon state change of input CTS. Cleared on an MSR
read.
0
0 No change detected on modem input, CTS.
1 State change detected on modem input, CTS.
1 DDSR Delta DSR.
Set upon state change of input DSR. Cleared on an MSR
read.
0
0 No change detected on modem input, DSR.
1 State change detected on modem input, DSR.
2 TERI Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an
MSR read.
0
0 No change detected on modem input, RI.
1 Low-to-high transition detected on RI.
3 DDCD Delta DCD. Set upon state change of input DCD. Cleared on
an MSR read.
0
0 No change detected on modem input, DCD.
1 State change detected on modem input, DCD.
4 CTS - Clear To Send State. Complement of input signal CTS. This
bit is connected to MCR[1] in modem loopback mode.
0
5 DSR - Data Set Ready State. Complement of input signal DSR.
This bit is connected to MCR[0] in modem loopback mode.
0
6 RI - Ring Indicator State. Complement of input RI. This bit is
connected to MCR[2] in modem loopback mode.
0
7 DCD - Data Carrier Detect State. Complement of input DCD. This
bit is connected to MCR[3] in modem loopback mode.
0
31:8 - - Reserved, the value read from a reserved bit is not defined. NA
Table 243. USART Scratch Pad Register (SCR - address 0x4000 801C) bit description
Bit Symbol Description Reset
Value
7:0 PAD A readable, writable byte. 0x00
31:8 - Reserved -
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