UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 254 of 523
NXP Semiconductors
UM10462
Chapter 12: LPC11U3x/2x/1x USART
3 FE Framing Error. When the stop bit of a received character is a
logic 0, a framing error occurs. A LSR read clears LSR[3]. The
time of the framing error detection is dependent on FCR0.
Upon detection of a framing error, the RX will attempt to
re-synchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the USART RBR FIFO.
0
0 Framing error status is inactive.
1 Framing error status is active.
4 BI Break Interrupt. When RXD1 is held in the spacing state (all
zeros) for one full character transmission (start, data, parity,
stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to
marking state (all ones). A LSR read clears this status bit. The
time of break detection is dependent on FCR[0].
Note: The break interrupt is associated with the character at
the top of the USART RBR FIFO.
0
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 THRE Transmitter Holding Register Empty. THRE is set immediately
upon detection of an empty USART THR and is cleared on a
THR write.
1
0 THR contains valid data.
1 THR is empty.
6 TEMT Transmitter Empty. TEMT is set when both THR and TSR are
empty; TEMT is cleared when either the TSR or the THR
contain valid data.
1
0 THR and/or the TSR contains valid data.
1 THR and the TSR are empty.
7 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX
error such as framing error, parity error or break interrupt, is
loaded into the RBR. This bit is cleared when the LSR register
is read and there are no subsequent errors in the USART
FIFO.
0
0 RBR contains no USART RX errors or FCR[0]=0.
1 USART RBR contains at least one USART RX error.
8 TXERR Tx Error. In smart card T=0 operation, this bit is set when the
smart card has NACKed a transmitted character, one more
than the number of times indicated by the TXRETRY field.
0
31:9 - - Reserved -
Table 241. USART Line Status Register Read only (LSR - address 0x4000 8014) bit
description
…continued
Bit Symbol Value Description Reset
Value
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