UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 51 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
Remark: Do not set the LOCK bit in the WWDT MOD register (Table 337 ) when the IRC is
selected as a clock source for the WWDT. This prevents the part from entering the
Power-down mode correctly.
Power-down mode eliminates all power used by analog peripherals and all dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses. The processor state and registers, peripheral registers, and internal SRAM values
are maintained, and the logic levels of the pins remain static. Wake-up times are longer
compared to the Deep-sleep mode.
3.9.5.1 Power configuration in Power-down mode
Power consumption in Power-down mode can be configured by the power configuration
setting in the PDSLEEPCFG (Table 45
) register in the same way as for Deep-sleep mode
(see Section 3.9.4.1
):
• The watchdog oscillator can be left running in Deep-sleep mode if required for the
WWDT.
• The BOD circuit can be left running in Deep-sleep mode if required by the application.
3.9.5.2 Programming Power-down mode
The following steps must be performed to enter Power-down mode:
1. The PD bits in the PCON register must be set to 0x2 (Table 54
).
2. Select the power configuration in Power-down mode in the PDSLEEPCFG (Table 45
)
register.
3. If the lock bit 5 in the WWDT MOD register is set (Table 337
) and the IRC is selected
as the WWDT clock source, reset the part to clear the lock bit and then select the
watchdog oscillator as the WWDT clock source.
4. If the main clock is not the IRC, power up the IRC in the PDRUNCFG register and
switch the clock source to IRC in the MAINCLKSEL register (Table 21
). This ensures
that the system clock is shut down glitch-free.
5. Select the power configuration after wake-up in the PDAWAKECFG (Table 46
)
register.
6. If any of the available wake-up interrupts are used for wake-up, enable the interrupts
in the interrupt wake-up registers (Table 43
, Table 44) and in the NVIC.
7. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register.
8. Use the ARM WFI instruction.
3.9.5.3 Wake-up from Power-down mode
The microcontroller can wake up from Power-down mode in the same way as from
Deep-sleep mode:
• Signal on one of the eight pin interrupts selected in Table 40. Each pin interrupt must
also be enabled in the STARTERP0 register (Table 43
) and in the NVIC.
• BOD signal, if the BOD is enabled in the PDSLEEPCFG register:
– BOD interrupt using the interrupt wake-up register 1 (Table 44
). The BOD interrupt
must be enabled in the NVIC. The BOD interrupt must be selected in the
BODCTRL register.
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