UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 38 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
Setting this parameter to a very low value (e.g. zero) will guarantee the best possible
interrupt performance but will also introduce a significant degree of uncertainty and jitter.
Requiring the system to always take a larger number of cycles (whether it needs it or not)
will reduce the amount of uncertainty but may not necessarily eliminate it.
Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt
request within 15 cycles. System factors external to the cpu, however, bus latencies,
peripheral response times, etc. can increase the time required to complete a previous
instruction before an interrupt can be serviced. Therefore, accurately specifying a
minimum number of cycles that will ensure determinism will depend on the application.
The default setting for this register is 0x010.
3.5.33 NMI source selection register
The NMI source selection register selects a peripheral interrupts as source for the NMI
interrupt of the ARM Cortex-M0 core. For a list of all peripheral interrupts and their IRQ
numbers see Table 59
. For a description of the NMI functionality, see Section 24.3.3.2.
Remark: When you want to change the interrupt source for the NMI, you must first disable
the NMI source by setting bit 31 in this register to 0. Then change the source by updating
the IRQN bits and re-enable the NMI source by setting bit 31 to 1.
Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable
interrupts, and the selected interrupt is enabled, one interrupt request can result in both a
Non-Maskable and a normal interrupt. This can be avoided by disabling the normal
interrupt in the NVIC, as described in Section 24.5.2
.
3.5.34 Pin interrupt select registers
Each of these 8 registers selects one GPIO pin from all GPIO pins on both ports as the
source of a pin interrupt. To select a pin for any of the eight pin interrupts, write the pin
number as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55 for pins PIO1_0 to PIO1_31
to the INTPIN bits. For example, setting INTPIN to 0x5 in PINTSEL0 selects pin PIO0_5
for pin interrupt 0. Setting INTPIN in PINTSEL7 to 0x32 (pin 50) selects pin PIO1_26 for
pin interrupt 7.
Table 38. IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description
Bit Symbol Description Reset
value
7:0 LATENCY 8-bit latency value 0x010
31:8 - Reserved -
Table 39. NMI source selection register (NMISRC, address 0x4004 8174) bit description
Bit Symbol Description Reset
value
4:0 IRQN The IRQ number of the interrupt that acts as the Non-Maskable Interrupt
(NMI) if bit 31 is 1. See Table 59
for the list of interrupt sources and their
IRQ numbers.
0
30:5 - Reserved -
31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source
selected by bits 4:0.
0
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