UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 377 of 523
NXP Semiconductors
UM10462
Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)
17.8.7 Watchdog Timer Window register
The WDWINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed sequence occurs when WDTV is greater than the value in
WDWINDOW, a watchdog event will occur.
WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
17.9 Watchdog timing examples
The following figures illustrate several aspects of Watchdog Timer operation.
Table 343. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit
description
Bit Symbol Description Reset
Value
9:0 WARNINT Watchdog warning interrupt compare value. 0
31:10 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 344. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description
Bit Symbol Description Reset
Value
23:0 WINDOW Watchdog window value. 0xFF FFFF
31:24 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Fig 65. Early Watchdog Feed with Windowed Mode Enabled
125A 12581259 1257
WDCLK / 4
Watchdog
Counter
Early Feed
Event
Watchdog
Reset
Conditions:
WINDOW = 0x1200
WARNINT = 0x3FF
TC = 0x2000
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