UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 242 of 523
12.1 How to read this chapter
The USART controller is available on all LPC11U3x/2x/1x parts.
12.2 Basic configuration
The USART is configured as follows:
• Pins: The USART pins must be configured in the corresponding IOCON registers (see
Section 7.4
).
• The USART block is enabled through the SYSAHBCLKCTRL register (see Table 24).
• The peripheral USART clock (PCLK), which is used by the USART baud rate
generator, is controlled by the UARTCLKDIV register (see Table 26
).
12.3 Features
• 16-byte receive and transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Software or hardware flow control.
• RS-485/EIA-485 9-bit mode support with output enable.
• RTS/CTS flow control and other modem control signals.
• 1X-clock send or receive.
• ISO 7816-3 compliant smart card interface.
• IrDA interface.
12.4 Pin description
UM10462
Chapter 12: LPC11U3x/2x/1x USART
Rev. 5.5 — 21 December 2016 User manual
Table 228. USART pin description
Pin Type Description
RXD Input Serial Input. Serial receive data.
TXD Output Serial Output. Serial transmit data (input/output in smart card mode).
RTS
Output Request To Send. RS-485 direction control pin.
CTS
Input Clear To Send.
DTR
Output Data Terminal Ready.
DSR
Input Data Set Ready. (Not available on HVQFN33-pin packages).
DCD
Input Data Carrier Detect.
RI
Input Ring Indicator. (Not available on HVQFN33-pin packages).
SCLK I/O Serial Clock.
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