UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 4 of 523
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UM10462
LPC11U3x/2x/1x User manual
4.1 20130719 Modifications:
• Description of the NMISRC register updated. See Section 3.5.32 “NMI source selection
register”.
• Bootloader description clarified. See Section 20.2.
• Code listings corrected in Chapter 10.
• Table 346 “LPC11U3x flash sectors and pages” corrected for LPC11U35 parts.
• Editorial updates in Section 20.14 “IAP commands”.
• Steps to enter Deep-sleep mode and Power-down mode updated in Section 3.9.4.2
“Programming Deep-sleep mode” and Section 3.9.5.2 “Programming Power-down
mode”: Main clock must be switched to IRC before entering either mode.
• Minimum USB AHB clock changed to 6 MHz. See Section 11.4.7.
• Description of ISP GO command expanded. See Section 20.13.8.
4 20121119 Modifications:
• Removed remark “USB ISP commands are supported for the Windows operating
system only.”. USP ISP commands are supported in Windows, Linux, and Mac OS.
• Remove the following step to execute before entering Deep power-down: Enable the
IRC. This step is not longer required. See Section 3.9.6 “Deep power-down mode”.
• Register offset of the CR1 register corrected in timers CT16B0 and CT32B0. See
Table 293 and Table 314.
• Bit position of the CAP1 interrupt flag corrected in the IR registers of timers CT16B0
and CT32B0. See Table 282 and Table 303.
• Bit positions of the CAP1 edge and interrupt control bits corrected in the CCR registers
of timers CT16B0 and CT32B0. See Table 290 and Table 311.
• Bit values of the CAP1 counter mode and capture input select bits corrected in the
CTCR registers of timers CT16B0 and CT32B0. See Table 297 and Table 319.
• Remove instruction breakpoints from feature list for SWD. See Section 21.2.
• Explained use of interrupts with Power profiles in Section 5.3 “General description”.
• BOD interrupt level 0 removed. See Section 3.5.29 “BOD control register”.
• Polarity of the IOCON glitch filter FILTR bit changed: 0 = glitch filter on, 1 = glitch filter
off. See Table 60.
• Reset value of SYSCON registers updated and reset value after boot added. See
Table 5 “Register overview: system control block (base address 0x4004 8000)”.
3 20120716 Modifications:
• Parts LPC11U3x added.
• Editorial updates to Section 9.4.1 and Section 9.6.4.
• USB on-chip driver support for composite device added in Chapter 10.
Revision history …continued
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