NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 32 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
8 CT16B1 Enables clock for 16-bit counter/timer 1. 0
0 Disable
1 Enable
9 CT32B0 Enables clock for 32-bit counter/timer 0. 0
0 Disable
1 Enable
10 CT32B1 Enables clock for 32-bit counter/timer 1.
0 Disable
1 Enable
11 SSP0 Enables clock for SSP0. 0
0 Disable
1 Enable
12 USART Enables clock for UART.
0 Disable
1 Enable
13 ADC Enables clock for ADC. 0
0 Disable
1 Enable
14 USB Enables clock to the USB register interface. 0
0 Disable
1 Enable
15 WWDT Enables clock for WWDT. 0
0 Disable
1 Enable
16 IOCON Enables clock for I/O configuration block. 0
0 Disable
1 Enable
17 - Reserved 0
18 SSP1 Enables clock for SSP1. 0
0 Disable
1 Enable
19 PINT Enables clock to GPIO Pin interrupts register
interface.
0
0 Disable
1 Enable
22:20 - Reserved -
23 GROUP0INT Enables clock to GPIO GROUP0 interrupt register
interface.
0
0 Disable
1 Enable
Table 24. System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
…continued
Bit Symbol Value Description Reset
value