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User manual Rev. 5.5 — 21 December 2016 341 of 523
NXP Semiconductors
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
Table 305. Capture Control Register (CCR, address 0x4000 C028 (CT16B0)) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
1 CAP0FE Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
2 CAP0I Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
3- Reserved. -
4- Reserved. -
5- Reserved. -
6 CAP1RE Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will
cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1
CT16B1.
0
1 Enabled.
0 Disabled.
7 CAP1FE Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will
cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1
CT16B1.
0
1 Enabled.
0 Disabled.
8 CAP1I Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will
generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1.
0
1 Enabled.
0 Disabled.
31:9 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 306. Capture Control Register (CCR, address 0x4001 0028 (CT16B1)) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
1 CAP0FE Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.