UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 359 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
6 CAP1RE Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
7 CAP1FE Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
8 CAP1I Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
31:9 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 326: Capture Control Register (CCR, address 0x4001 4028 (CT32B0) ) bit description
Bit Symbol Value Description Reset
value
Table 327: Capture Control Register (CCR, address 0x4001 8028 (CT32B1)) bit description
Bit Symbol Value Description Reset
value
0 CAP0RE Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
1 CAP0FE Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
2 CAP0I Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will
generate an interrupt.
0
1 Enabled.
0 Disabled.
3 CAP1RE Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
4 CAP1FE Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will
cause CR1 to be loaded with the contents of TC.
0
1 Enabled.
0 Disabled.
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