NXP Semiconductors LPC11U3x

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User manual Rev. 5.5 — 21 December 2016 28 of 523

NXP Semiconductors

UM10462

Chapter 3: LPC11U3x/2x/1x System control block

Table 17. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

bit description

Bit Symbol Value Description Reset

value

1:0 SEL System PLL clock source 1

0x0 IRC

0x1 Crystal Oscillator (SYSOSC)

0x2 Reserved

0x3 Reserved

31:2 - - Reserved -

Main Page

Chapter 1: Lpc11U3X/2X/1X Introductory Information6
Introduction6
Features6
Chapter 25 : Supplementary Information8
Ordering Information8
Block Diagram11
How to Read this Chapter14
Memory Map15
Chapter 2: Lpc11U3X/2X/1X Memory Mapping16
Chapter 3: Lpc11U3X/2X/1X System Control Block19
How to Read this Chapter19
Introduction19
Pin Description19
Clocking and Power Control19
Register Description20
- System Memory Remap Register22
- Peripheral Reset Control Register23
- System PLL Control Register23
- System PLL Status Register24
- USB PLL Control Register24
- USB PLL Status Register25
- System Oscillator Control Register25
- Watchdog Oscillator Control Register26
- Internal Resonant Crystal Control Register27
- System Reset Status Register27
- System PLL Clock Source Select Register27
- System PLL Clock Source Update Register29
- USB PLL Clock Source Select Register29
- USB PLL Clock Source Update Enable Register29
- Main Clock Source Select Register30
- Main Clock Source Update Enable Register30
- System Clock Divider Register30
- System Clock Control Register31
- SSP0 Clock Divider Register33
- USART Clock Divider Register33
- SSP1 Clock Divider Register34
- USB Clock Source Select Register34
- USB Clock Source Update Enable Register34
- USB Clock Divider Register35
- CLKOUT Clock Source Select Register35
- CLKOUT Clock Source Update Enable Register35
- CLKOUT Clock Divider Register36
- POR Captured PIO Status Register 036
- POR Captured PIO Status Register 136
- BOD Control Register36
- System Tick Counter Calibration Register37
- IRQ Latency Register37
- NMI Source Selection Register38
- Pin Interrupt Select Registers38
- USB Clock Control Register39
- USB Clock Status Register39
- Interrupt Wake-Up Enable Register 040
- Interrupt Wake-Up Enable Register 140
- Deep-Sleep Mode Configuration Register41
- Wake-Up Configuration Register42
- Power Configuration Register43
- Device ID Register44
- Flash Memory Access45
Reset45
Start-Up Behavior46
Brown-Out Detection46
Power Management47
- Reduced Power Modes and WWDT Lock Features47
- Active Mode48
- Power Configuration in Active Mode48
- Sleep Mode48
- Power Configuration in Sleep Mode48
- Programming Sleep Mode48
- Wake-Up from Sleep Mode49
- Deep-Sleep Mode49
- Power Configuration in Deep-Sleep Mode49
- Programming Deep-Sleep Mode49
- Wake-Up from Deep-Sleep Mode50
- Power-Down Mode50
- Power Configuration in Power-Down Mode51
- Programming Power-Down Mode51
- Wake-Up from Power-Down Mode51
- Deep Power-Down Mode52
  - Mode52
- Programming Deep Power-Down Mode52
- Wake-Up from Deep Power-Down Mode53
System PLL/USB PLL Functional Description53
- Lock Detector54
- Power-Down Control54
- Divider Ratio Programming54
- Frequency Selection55
- Normal Mode55
- Power-Down Mode55
Chapter 4: Lpc11U3X/2X/1X Power Management Unit (PMU)56
How to Read this Chapter56
Introduction56
Register Description56
- Power Control Register56
- General Purpose Registers 0 to 357
- General Purpose Register 457
Functional Description58
Chapter 5: Lpc11U3X/2X/1X Power Profiles59
How to Read this Chapter59
Features59
Basic Configuration59
General Description59
Definitions61
Clocking Routine61
- Set_Pll61
- Param0: System PLL Input Frequency and Param1: Expected System Clock62
- Param2: Mode62
- Param3: System PLL Lock Time-Out62
- Code Examples63
- Invalid Frequency63
  - Exceeded)63
- Invalid Frequency Selection63
  - Restrictions)63
- Exact Solution Cannot be Found (PLL)63
  - Value64
  - Expected Value64
Power Routine64
- Set_Power64
- Param0: Main Clock66
- Param1: Mode66
- Param2: System Clock66
- Code Examples66
  - Exceeded)66
- An Applicable Power Setup66
Chapter 6: Lpc11U3X/2X/1X NVIC68
How to Read this Chapter68
Introduction68
Features68
Interrupt Sources68
Register Description70
- Interrupt Set Enable Register 0 Register71
- Interrupt Clear Enable Register 072
- Interrupt Set Pending Register 0 Register73
- Interrupt Clear Pending Register 0 Register74
- Interrupt Active Bit Register 075
- Interrupt Priority Register 076
- Interrupt Priority Register 177
- Interrupt Priority Register 277
- Interrupt Priority Register 377
- Interrupt Priority Register 478
- Interrupt Priority Register 578
- Interrupt Priority Register 678
- Interrupt Priority Register 779
How to Read this Chapter80
Introduction80
General Description80
Chapter 7: Lpc11U3X/2X/1X I/O Configuration81
- Pin Function81
- Pin Mode81
- Hysteresis82
- Input Inverter82
- Input Glitch Filter82
- Open-Drain Mode82
- Analog Mode82
- C Mode82
- RESET Pin (Pin RESET_PIO0_0)83
- WAKEUP Pin (Pin PIO0_16)83
Register Description84
- I/O Configuration Registers86
- RESET_PIO0_0 Register86
- PIO0_1 Register87
- PIO0_2 Register88
- PIO0_3 Register88
- PIO0_4 Register89
- PIO0_5 Register89
- PIO0_6 Register90
- PIO0_7 Register91
- PIO0_8 Register91
- PIO0_9 Register92
- SWCLK_PIO0_10 Register93
- TDI_PIO0_11 Register94
- TMS_PIO0_12 Register95
- PIO0_13 Register96
- TRST_PIO0_14 Register97
- SWDIO_PIO0_15 Register98
- PIO0_16 Register99
- PIO0_17 Register100
- PIO0_18 Register100
- PIO0_19 Register101
- PIO0_20 Register102
- PIO0_21 Register103
- PIO0_22 Register103
- PIO0_23 Register104
- PIO1_0 Register105
- PIO1_1 Register106
- PIO1_2 Register107
- PIO1_3 Register107
- PIO1_4 Register108
- PIO1_5 Register109
- PIO1_6 Register109
- PIO1_7 Register110
- PIO1_8 Register111
- PIO1_9 Register112
- PIO1_10 Register112
- PIO1_11 Register113
- PIO1_12 Register114
- PIO1_13 Register114
- PIO1_14 Register115
- PIO1_15 Register116
- PIO1_16 Register117
- PIO1_17 Register117
- PIO1_18 Register118
- PIO1_19 Register119
- PIO1_20 Register120
- PIO1_21 Register120
- PIO1_22 Register121
- PIO1_23 Register122
- PIO1_24 Register123
- PIO1_25 Register123
- PIO1_26 Register124
- PIO1_27 Register125
- PIO1_28 Register125
- PIO1_29 Register126
- PIO1_31 Register127
Chapter 8: Lpc11U3X/2X/1X Pin Configuration128
How to Read this Chapter128
Pin Configuration129
- Lpc11U1X Pin Description132
- Lpc11U2X Pin Description139
- Lpc11U3X Pin Description145
Chapter 9: Lpc11U3X/2X/1X GPIO153
How to Read this Chapter153
Basic Configuration153
Features153
- GPIO Pin Interrupt Features153
- GPIO Group Interrupt Features153
- GPIO Port Features154
Introduction154
- GPIO Pin Interrupts154
- GPIO Group Interrupt154
- GPIO Port154
Register Description154
- GPIO Pin Interrupts Register Description157
- Pin Interrupt Mode Register157
- Pin Interrupt Level (Rising Edge) Interrupt Enable Register157
- Pin Interrupt Level (Rising Edge) Interrupt Set Register157
- Pin Interrupt Level (Rising Edge Interrupt) Clear Register158
- Pin Interrupt Active Level (Falling Edge) Interrupt Enable Register158
- Pin Interrupt Active Level (Falling Edge) Interrupt Set Register159
- Pin Interrupt Active Level (Falling Edge Interrupt) Clear Register159
- Pin Interrupt Rising Edge Register160
- Pin Interrupt Falling Edge Register160
- Pin Interrupt Status Register161
- GPIO GROUP0/GROUP1 Interrupt Register Description161
- Grouped Interrupt Control Register161
- GPIO Grouped Interrupt Port Polarity Registers161
- GPIO Grouped Interrupt Port Enable Registers162
- GPIO Port Register Description163
- GPIO Port Byte Pin Registers163
- GPIO Port Word Pin Registers163
- GPIO Port Direction Registers164
- GPIO Port Mask Registers164
- GPIO Port Pin Registers165
- GPIO Masked Port Pin Registers165
- GPIO Port Set Registers166
- GPIO Port Clear Registers166
- GPIO Port Toggle Registers166
Functional Description167
- Reading Pin State167
- GPIO Output167
- Masked I/O168
- GPIO Interrupts168
- Pin Interrupts168
- Group Interrupts169
- Recommended Practices169
Chapter 10 : Lpc11U3X/2X/1X USB On-Chip Drivers170
How to Read this Chapter170
Introduction170
USB Driver Functions170
Usb Api172
- Bm_T172
  - Descriptor173
- Cdc_Header_Descriptor173
- Cdc_Line_Coding173
- Cdc_Union_1Slave_Descriptor174
- Cdc_Union_Descriptor174
- Dfu_Status174
- Hid_Descriptor174
- Hid_Report_T175
- Msc_Cbw176
- Msc_Csw176
- Request_Type176
- Usb_Common_Descriptor176
- Usb_Core_Descs_T177
- Usb_Device_Qualifier_Descriptor 177 _Usb_Dfu_Func_Descriptor177
- Usb_Interface_Descriptor178
- Usb_Other_Speed_Configuration 178 _Usb_Setup_Packet179
- Usb_String_Descriptor179
- Wb_T180
- Usbd_Api180
- Usbd_Api_Init_Param181
- Usbd_Cdc_Api184
- Usbd_Cdc_Init_Param185
- Usbd_Core_Api194
- Usbd_Dfu_Api197
- Usbd_Dfu_Init_Param198
- Usbd_Hid_Api200
- Usbd_Hid_Init_Param201
- Usbd_Hw_Api207
- Usbd_Msc_Api215
- Usbd_Msc_Init_Param216
Chapter 11: Lpc11U3X/2X/1X USB2.0 Device Controller221
How to Read this Chapter221
Basic Configuration221
Features221
General Description221
- USB Software Interface223
- Fixed Endpoint Configuration223
- Softconnect223
- Interrupts224
- Suspend and Resume224
- Frame Toggle Output224
- Clocking225
Pin Description225
Register Description225
- USB Device Command/Status Register225
- USB EP Command/Status List Start Address225
- USB Data Buffer Start Address225
- USB Link Power Management Register225
- USB Info Register (INFO)228
- USB Endpoint Skip (EPSKIP)230
- USB Endpoint Buffer in Use (EPINUSE)230
- USB Interrupt Status Register (INTSTAT)231
- USB Interrupt Enable Register (INTEN)232
- USB Set Interrupt Status Register233
- USB Interrupt Routing Register233
  - (Introuting)233
- USB Endpoint Toggle (EPTOGGLE)233
Functional Description234
- Endpoint Command/Status List234
- Control Endpoint 0237
- Generic Endpoint: Single-Buffering238
  - Generic Endpoint: Double-Buffering239
- Special Cases239
- Use of the Active Bit239
  - Generation of a STALL Handshake239
- Clear Feature (Endpoint Halt)239
  - Set Configuration240
- USB Wake-Up240
  - Waking up from Deep-Sleep and Power-Down Modes on USB Activity240
- Remote Wake-Up240
Chapter 12 : Lpc11U3X/2X/1X USART242
How to Read this Chapter242
Basic Configuration242
Features242
Pin Description242
Register Description243
- USART Receiver Buffer Register (When DLAB = 0, Read Only)244
- USART Transmitter Holding Register244
  - DLAB = 0, Write Only)244
- USART Divisor Latch LSB and MSB Registers245
  - (When DLAB = 1)245
- USART Interrupt Enable Register245
  - Dlab = 0)245
- USART Interrupt Identification Register246
  - Only)248
- USART FIFO Control Register (Write Only)248
- USART Line Control Register249
- USART Modem Control Register250
- Auto-Flow Control251
- Auto-RTS251
- Auto-CTS252
- USART Line Status Register (Read-Only)253
- USART Modem Status Register255
- USART Scratch Pad Register255
- USART Auto-Baud Control Register256
- Auto-Baud256
- Auto-Baud Modes257
- Irda Control Register258
- USART Fractional Divider Register260
- Baud Rate Calculation261
- Example 1: UART_PCLK = 14.7456 Mhz, BR263
- Example 2: UART_PCLK = 12.0 Mhz, BR = 115200263
- USART Oversampling Register263
- USART Transmit Enable Register264
- UART Half-Duplex Enable Register265
- Smart Card Interface Control Register265
- USART RS485 Control Register266
- USART RS-485 Address Match Register267
- USART RS-485 Delay Value Register267
- USART Synchronous Mode Control Register 268 Functional Description270
- RS-485/EIA-485 Modes of Operation270
  - RS-485/EIA-485 Normal Multidrop Mode270
  - Mode270
  - RS-485/EIA-485 Auto Direction Control271
  - RS485/EIA-485 Driver Delay Time271
  - RS485/EIA-485 Output Inversion271
- Smart Card Mode271
- Smart Card Set-Up Procedure272
Architecture273
Chapter 13: Lpc11U3X/2X/1X SSP/SPI275
How to Read this Chapter275
Basic Configuration275
Features275
General Description275
Pin Description276
Register Description276
- SSP/SPI Control Register 0277
- SSP/SPI Control Register 1278
- SSP/SPI Data Register279
- SSP/SPI Status Register280
- SSP/SPI Clock Prescale Register280
- SSP/SPI Interrupt Mask Set/Clear Register280
- SSP/SPI Raw Interrupt Status Register281
- SSP/SPI Masked Interrupt Status Register281
- SSP/SPI Interrupt Clear Register282
Functional Description282
- Texas Instruments Synchronous Serial Frame Format282
- SPI Frame Format283
  - Control283
- SPI Format with CPOL=0,CPHA=0284
- SPI Format with CPOL=0,CPHA=1285
- SPI Format with CPOL = 1,CPHA = 0285
- SPI Format with CPOL = 1,CPHA = 1287
- Semiconductor Microwire Frame Format287
- Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode289
Chapter 14: Lpc11U3X/2X/1X I2C-Bus Controller290
How to Read this Chapter290
Basic Configuration290
Features290
Applications290
General Description290
- I 2 C Fast-Mode Plus291
Pin Description292
Register Description292
- I 2 C Control Set Register (CONSET)293
- I 2 C Status Register (STAT)295
- I 2 C Data Register (DAT)295
- I 2 C Slave Address Register 0 (ADR0)296
- C SCL HIGH and LOW Duty Cycle Registers (SCLH and SCLL)296
  - Cycle296
  - I 2 C Control Clear Register (CONCLR)297
    - I 2 C Monitor Mode Control Register (MMCTRL) 297 Interrupt in Monitor Mode298
- Loss of Arbitration in Monitor Mode299
  - I 2 C Slave Address Registers (ADR[1, 2, 3]) . 299 I 2 C Data Buffer Register (DATA_BUFFER)299
  - I 2 C Mask Registers (MASK[0, 1, 2, 3])300
Functional Description300
- Input Filters and Output Stages301
- Address Registers, ADR0 to ADR3302
- Address Mask Registers, MASK0 to MASK3302
- Comparator302
- Shift Register, DAT302
- Arbitration and Synchronization Logic302
- Serial Clock Generator303
- Timing and Control304
- Control Register, CONSET and CONCLR304
- Status Decoder and Status Register304
C Operating Modes304
- Master Transmitter Mode304
- Master Receiver Mode305
- Slave Receiver Mode306
- Slave Transmitter Mode307
Details of I C Operating Modes307
- Master Transmitter Mode308
- Master Receiver Mode312
- Slave Receiver Mode315
- Slave Transmitter Mode319
- Miscellaneous States321
- STAT = 0Xf8321
- STAT = 0X00321
- Some Special Cases322
- Simultaneous Repeated START Conditions from322
  - Two Masters322
- Data Transfer after Loss of Arbitration323
- Forced Access to the I323
  - Bus323
- C-Bus Obstructed by a LOW Level on SCL or SDA324
- Bus Error324
- C State Service Routines324
- Initialization325
- C Interrupt Service325
- The State Service Routines325
- Adapting State Services to an Application325
Software Example325
- Initialization Routine325
- Start Master Transmit Function325
- Start Master Receive Function326
- I 2 C Interrupt Routine326
- Non Mode Specific States326
- State: 0X00326
- Master States326
- State: 0X08326
- State: 0X10327
- Master Transmitter States327
- State: 0X18327
- State: 0X20327
- State: 0X28327
- State: 0X30328
- State: 0X38328
- Master Receive States328
- State: 0X40328
- State: 0X48328
- State: 0X50328
- State: 0X58329
- Slave Receiver States329
- State: 0X60329
- State: 0X68329
- State: 0X70329
- State: 0X78330
- State: 0X80330
- State: 0X88330
- State: 0X90330
- State: 0X98331
- State: 0Xa0331
- Slave Transmitter States331
- State: 0Xa8331
- State: 0Xb0331
- State: 0Xb8331
- State: 0Xc0332
- State: 0Xc8332
Chapter 15: Lpc11U3X/2X/1X 16-Bit Counter/Timers CT16B0/1333
How to Read this Chapter333
Basic Configuration333
Features333
Applications334
General Description334
Pin Description334
Register Description334
- Interrupt Register337
- Timer Control Register337
- Timer Counter338
- Prescale Register338
- Prescale Counter Register338
- Match Control Register339
- Match Registers340
- Capture Control Register340
- Capture Registers342
- External Match Register343
- Count Control Register344
- PWM Control Register347
- Rules for Single Edge Controlled PWM Outputs348
Example Timer Operation349
Architecture349
Chapter 16 : Lpc11U3X/2X/1X 32-Bit Counter/Timers CT32B0/1351
How to Read this Chapter351
Basic Configuration351
Features351
Applications352
General Description352
Pin Description352
Register Description352
- Interrupt Register355
- Timer Control Register355
- Timer Counter Registers356
- Prescale Register356
- Prescale Counter Register356
- Match Control Register357
- Match Registers358
- Capture Control Register358
- Capture Registers360
- External Match Register360
- Count Control Register362
- PWM Control Register364
- Rules for Single Edge Controlled PWM Outputs365
Example Timer Operation366
Architecture367
Chapter 17: Lpc11U3X/2X/1X Windowed Watchdog Timer (WWDT)369
How to Read this Chapter369
Basic Configuration369
Features369
Applications370
Description370
- Block Diagram370
Clocking and Power Control371
Using the WWDT Lock Features372
- Accidental Overwrite of the WWDT Clock372
- Changing the WWDT Clock Source372
- Changing the WWDT Reload Value372
Register Description373
- Watchdog Mode Register373
- Watchdog Timer Constant Register375
- Watchdog Feed Register375
- Watchdog Timer Value Register376
- Watchdog Clock Select Register376
- Watchdog Timer Warning Interrupt Register . 376 Watchdog Timer Window Register377
Watchdog Timing Examples377
Chapter 18: Lpc11U3X/2X/1X System Tick Timer379
How to Read this Chapter379
Basic Configuration379
Features379
General Description379
Register Description380
- System Timer Control and Status Register380
- System Timer Reload Value Register381
- System Timer Current Value Register381
- System Timer Calibration Value Register382
Functional Description382
Example Timer Calculations382
- Example (System Clock = 50 Mhz)382
Chapter 19: Lpc11U3X/2X/1X ADC383
How to Read this Chapter383
Basic Configuration383
Features383
Pin Description383
Register Description384
- A/D Control Register (CR - 0X4001 C000)385
- A/D Global Data Register (GDR - 0X4001 C004)386
- A/D Interrupt Enable Register (INTEN - 0X4001 C00C)387
- A/D Data Registers (DR0 to DR7 - 0X4001 C010 to 0X4001 C02C)387
- A/D Status Register (STAT - 0X4001 C030) . 387 Operation388
- Hardware-Triggered Conversion388
- Interrupts388
- Accuracy Vs. Digital Receiver388
How to Read this Chapter389
Chapter 20: Lpc11U3X/2X/1X Flash Programming Firmware390
Bootloader390
Features390
Description390
Memory Map after any Reset391
Flash Content Protection Mechanism391
Criterion for Valid User Code392
ISP/IAP Communication Protocol393
- ISP Command Format393
- ISP Response Format393
- ISP Data Format393
- ISP Flow Control393
- ISP Command Abort393
- Interrupts During ISP393
- Interrupts During IAP394
- RAM Used by ISP Command Handler394
- RAM Used by IAP Command Handler394
USB Communication Protocol394
- Usage Note395
Boot Process Flowchart396
Sector Numbers397
- Lpc11U1X/2X397
- Lpc11U3X397
Code Read Protection (CRP)398
- ISP Entry Protection400
ISP Commands401
- Unlock <Unlock Code401
- Set Baud Rate <Baud Rate> <Stop Bit402

NXP Semiconductors LPC11U3x

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