UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 85 of 523
NXP Semiconductors
UM10462
Chapter 7: LPC11U3x/2x/1x I/O configuration
PIO0_20 R/W 0x050 I/O configuration for pin
PIO0_20/CT16B1_CAP0
0x0000 0090 Table 96
PIO0_21 R/W 0x054 I/O configuration for pin
PIO0_21/CT16B1_MAT0/MOSI1
0x0000 0090 Table 97
PIO0_22 R/W 0x058 I/O configuration for pin
PIO0_22/AD6/CT16B1_MAT1/MISO1
0x0000 0090 Table 98
PIO0_23 R/W 0x05C I/O configuration for pin
PIO0_23/AD7/IOH_9
0x0000 0090 Table 99
PIO1_0 R/W 0x060 I/O configuration for pin
PIO1_0/CT32B1_MAT0/IOH_10
0x0000 0090 Table 100
PIO1_1 R/W 0x064 I/O configuration for pin
PIO1_1/CT32B1_MAT1/IOH_11
0x0000 0090 Table 101
PIO1_2 R/W 0x068 I/O configuration for pin
PIO1_2/CT32B1_MAT2IOH_12
0x0000 0090 Table 102
PIO1_3 R/W 0x06C I/O configuration for pin
PIO1_3/CT32B1_MAT3/IOH_13
0x0000 0090 Table 103
PIO1_4 R/W 0x070 I/O configuration for pin
PIO1_4/CT32B1_CAP0/IOH_14
0x0000 0090 Table 104
PIO1_5 R/W 0x074 I/O configuration for pin
PIO1_5/CT32B1_CAP1/IOH_15
0x0000 0090 Table 105
PIO1_6 R/W 0x078 I/O configuration for pin PIO1_6/IOH_16 0x0000 0090 Table 106
PIO1_7 R/W 0x07C I/O configuration for pin PIO1_7/IOH_17 0x0000 0090 Table 107
PIO1_8 R/W 0x080 I/O configuration for pin PIO1_8/IOH_18 0x0000 0090 Table 108
PIO1_9 R/W 0x084 I/O configuration for pin PIO1_9 0x0000 0090 Table 109
PIO1_10 R/W 0x088 I/O configuration for pin PIO1_10 0x0000 0090 Table 110
PIO1_11 R/W 0x08C I/O configuration for pin PIO1_11 0x0000 0090 Table 111
PIO1_12 R/W 0x090 I/O configuration for pin PIO1_12 0x0000 0090 Table 112
PIO1_13 R/W 0x094 I/O configuration for pin
PIO1_13/DTR
/CT16B0_MAT0/TXD
0x0000 0090 Table 113
PIO1_14 R/W 0x098 I/O configuration for pin
PIO1_14/DSR/CT16B0_MAT1/RXD
0x0000 0090 Table 114
PIO1_15 R/W 0x09C I/O configuration for pin PIO1_15/DCD/
CT16B0_MAT2/SCK1
0x0000 0090 Table 115
PIO1_16 R/W 0x0A0 I/O configuration for pin
PIO1_16/RI
/CT16B0_CAP0
0x0000 0090 Table 116
PIO1_17 R/W 0x0A4 I/O configuration for
PIO1_17/CT16B0_CAP1/RXD
0x0000 0090 Table 117
PIO1_18 R/W 0x0A8 I/O configuration for
PIO1_18/CT16B1_CAP1/TXD
0x0000 0090 Table 118
PIO1_19 R/W 0x0AC I/O configuration for pin
PIO1_19/DTR
/SSEL1
0x0000 0090 Table 119
PIO1_20 R/W 0x0B0 I/O configuration for pin
PIO1_20/DSR
/SCK1
0x0000 0090 Table 120
PIO1_21 R/W 0x0B4 I/O configuration for pin
PIO1_21/DCD
/MISO1
0x0000 0090 Table 121
Table 75. Register overview: I/O configuration (base address 0x4004 4000) …continued
Name Access Address
offset
Description Reset value Reference
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