NXP Semiconductors LPC21 Series

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Overview

Function Description
Important Technical Specifications
Usage Features
Maintenance Features

The NXP LPC21xx and LPC22xx are 16/32-bit ARM7TDMI-S microcontrollers designed for various applications, including industrial control, medical systems, access control, and point-of-sale. They offer a balance of high performance, low power consumption, and a rich set of peripherals, all within compact 64-pin and 144-pin packages.

Function Description:

At their core, these microcontrollers feature an ARM7TDMI-S CPU with real-time emulation and embedded trace support. This CPU is based on Reduced Instruction Set Computer (RISC) principles, offering high instruction throughput and efficient real-time interrupt response. A key architectural feature is THUMB mode, which uses a 16-bit instruction set to reduce code size by over 30% with minimal performance impact, making it suitable for memory-constrained applications.

The LPC21xx/LPC22xx architecture includes a 128-bit wide internal memory interface and a unique accelerator architecture, enabling 32-bit code execution at the maximum clock rate. Peripherals are connected via an AMBA Advanced High-performance Bus (AHB) for the interrupt controller and an ARM Peripheral Bus (APB) for other on-chip functions. The Pin Connect Block allows flexible mapping of on-chip peripherals to device pins, configurable by software to meet specific application needs.

Important Technical Specifications:

CPU: 16/32-bit ARM7TDMI-S with real-time emulation and embedded trace support.
Memory:
- Flash Memory: 64/128/256 kB of embedded high-speed flash program memory. Flashless versions (LPC2210/20/90) are also available.
- SRAM: 8/16/64 kB of on-chip static RAM.
- Memory Interface: 128-bit wide internal memory interface.
Clock Speed:
- Maximum CPU clock: 60 MHz from a programmable on-chip PLL (input frequency 10 MHz to 25 MHz, settling time 100 ms).
- For flashless parts (LPC2210/20/90), maximum CPU clock can be 60 MHz (LPC2210/90), 72 MHz (LPC2290/01), or 75 MHz (LPC2210/01 and LPC2220) from PLL (settling time 100 µs).
- On-chip integrated oscillator: Operates with external crystal (1 MHz to 25 MHz) or external oscillator (up to 50 MHz).
I/O:
- GPIO: Up to 48 (64-pin packages) or 112 (144-pin packages) 5 V tolerant fast general purpose I/O pins.
- External Interrupts: Up to 12 edge or level sensitive external interrupt pins.
Timers/Counters: Two 32-bit timers/external event counters, each with four capture and four compare channels.
PWM: PWM unit with up to 6 outputs.
RTC: Real Time Clock.
Watchdog: Watchdog timer.
ADC: 10-bit A/D converter with four/eight analog inputs, conversion times as low as 2.44 ms per channel, and dedicated result registers.
Communication Interfaces:
- UART: Two UARTs (16C550 compatible).
- I2C-bus: Fast I2C-bus (400 kbit/s).
- SPI: Two SPI interfaces.
- SSP: Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats (enhanced parts).
- CAN: Up to four interconnected CAN interfaces with advanced acceptance filters.
Interrupt Controller: Vectored interrupt controller with configurable priorities and vector addresses.
Power Supply:
- CPU operating voltage: 1.65 V to 1.95 V (1.8 V ± 8.3 %).
- I/O power supply: 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
Packages: Compact 64-pin and 144-pin packages (LQFP and TFBGA).

Usage Features:

Memory Accelerator Module (MAM): Maximizes ARM processor performance when running code from flash memory using a dual flash bank. It includes prefetch buffers and branch trail buffers to minimize CPU fetch stalls. MAM can operate in three modes: off, partially enabled, and fully enabled, trading performance for predictability.
External Memory Controller (EMC): (Available in 144-pin packages only) Supports various static memory-mapped devices (RAM, ROM, flash, external I/O) with independent configuration for up to four banks, each up to 16 MB. It offers programmable bus turnaround, read/write WAIT states, burst mode operation, and write protection.
Vectored Interrupt Controller (VIC): Manages 32 interrupt request inputs, assigning them to FIQ (highest priority), vectored IRQ (middle priority, 16 slots), and non-vectored IRQ (lowest priority) categories. Priorities can be dynamically assigned and adjusted.
System Control Block: Includes functions for crystal oscillator, external interrupt inputs, memory mapping control, PLL, power control, reset, APB divider, and wakeup timer.
GPIO: Fast GPIO ports (enhanced parts) enable port pin toggling up to 3.5 times faster than original devices and allow reading pin state regardless of function. Legacy GPIO is also supported for backward compatibility.
UART (UART0/1): Enhanced parts include a fractional baud rate generator for fine-tuning baud rates, auto-bauding capabilities, and hardware flow control (auto-CTS/RTS).
SSP: (Enhanced parts) Buffered serial controller with programmable data length and master mode enhancements.
ADC: Dedicated result registers reduce interrupt overhead. ADC pads are 5 V tolerant when configured for digital I/O.
Power Saving Modes: Two modes: Idle (CPU suspended, peripherals active) and Power-down (oscillator shut down, no internal clocks). Processor wake-up from Power-down mode via external interrupt or CAN controllers.
Peripheral Clock Scaling: Individual enable/disable of peripheral functions for additional power optimization.

Maintenance Features:

In-System Programming (ISP): Allows programming or reprogramming of on-chip flash memory using boot loader software and a serial port (UART0).
In-Application Programming (IAP): Enables the application program to erase and/or program the flash memory during runtime.
JTAG Interface: Serial built-in JTAG interface for programming and debugging. Debug tools can write flash images to RAM and then use IAP calls to program flash.
Code Read Protection (CRP): A mechanism to enable different security levels, restricting access to on-chip Flash and ISP to protect application code from observation. CRP levels can disable JTAG access, restrict ISP commands, or disable ISP entry via the P0.14 pin.
Flash Memory Reliability: Minimum of 100,000 erase/write cycles and 20 years of data retention.
Error Correction Code (ECC): Flash memory is equipped with ECC for single-bit error correction with Hamming code, transparent to the running application. Data must be written in groups of 16 bytes for proper ECC operation.
Reset Logic: Assertion of chip reset by any source starts a wakeup timer, ensuring the oscillator and other analog functions are fully functional before CPU execution. The RESET pin has a Schmitt trigger input with a glitch filter.