UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 2 of 523
NXP Semiconductors
UM10462
LPC11U3x/2x/1x User manual
Revision history
Rev Date Description
5.5 20161221 Modifications:
• Updated Table 200 “USBD_API_INIT_PARAM class structure” with:
Parameters:
a. hUsb = Handle to the USB device stack.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.
• Updated Table 208 “USBD_HW_API class structure”:
Added GetMemSize to the text: This function is called by application layer before calling
pUsbApi->hw->
Added Parameters:
– hUsb = Handle to the USB device stack.
– EPNum = Endpoint number corresponding to the event as per USB specification. ie.
An EP1_IN isrepresented by 0x81 number. For device events set this param to 0x0.
– event = Type of endpoint event. See USBD_EVENT_T for more details.
– enable = 1 - enable event, 0 - disable event.Returns:Returns ErrorCode_t type to
indicate success or error condition.Return values:1. LPC_OK(0) = - On success2.
ERR_USBD_INVALID_REQ(0x00040001) = - Invalid event type.
• Added on-chip local RAM to Section 20.8.8 “RAM used by ISP command handler”,
Section 20.8.9 “RAM used by IAP command handler”
, and Section 20.14 “IAP
commands”
• Deleted: The boot sector can not be prepared by this command from Section 20.14.1
“Prepare sector(s) for write operation”, Table 384 “IAP Copy RAM to flash command”,
and Table 385 “IAP Erase Sector(s) command”.
5.4 20161007 Modifications:
• Added text after Table 227 “Endpoint commands”: For EP0 transfers, the hardware will
do auto handshake as long as the ACTIVE bit is set in EP0_IN/OUT command list.
Unlike other endpoints, the hardware will not clear the ACTIVE bit after transfer is done.
Thus, the software should manually clear the bit whenever it receives new setup packet
and set it only after it has queued the data for control transfer.
5.3 20140611 Modifications:
• I/O Handler interrupt added in Table 59 “Connection of interrupt sources to the Vectored
Interrupt Controller”.
• NVIC register description added. See Section 6.5.
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