NXP Semiconductors MPC5777M - Page 105

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 105
3.16.2.1.4 DSPI Master Mode – Output Only
Table 55. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock
1,2
1
All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS
with pad driver strength as defined. Timing may degrade for weaker output drivers.
2
TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
# Symbol Characteristic
Condition Value
Unit
Pad drive Load Min Max
1t
SCK
CC SCK cycle time LVDS 15 pF
to 50 pF
differential
25.0 — ns
2t
CSV
CC PCS valid after SCK
3
(SCK with 50 pF
differential load cap.)
3
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of
DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.
Very strong 25 pF — 6.0 ns
Strong 50 pF — 10.5 ns
3t
CSH
CC PCS hold after SCK
3
(SCK with 50 pF
differential load cap.)
Very strong 0pF –4.0 — ns
Strong 0pF –4.0 —ns
4t
SDC
CC SCK duty cycle
(SCK with 50 pF
differential load cap.)
LVDS 15 pF
to 50 pF
differential
1
/
2
t
SCK
–2
1
/
2
t
SCK
+2 ns
SOUT data valid time (after SCK edge)
5t
SUO
CC SOUT data valid time
from SCK
4
SOUT and SCK drive strength
LVDS 15 pF
to 50 pF
differential
—3.5ns
SOUT data hold time (after SCK edge)
6t
HO
CC SOUT data hold time
after SCK
4
4
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
SOUT and SCK drive strength
LVDS 15 pF
to 50 pF
differential
–3.5 — ns
Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock
1,2
# Symbol Characteristic
Condition Value
3
Unit
Pad drive
4
Load (C
L
)Min Max
1t
SCK
CC SCK cycle time SCK drive strength
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 — ns
Medium 50 pF 200.0 — ns