NXP Semiconductors MPC5777M - Page 103

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 103
8
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 54. DSPI LVDS slave timing – full duplex – modified transfer format (MTFE = 0/1)
1
1
DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that
case only.
# Symbol Characteristic
Condition Value
Unit
Pad drive Load Min Max
1t
SCK
CC SCK cycle time
2
2
Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
— — 62 — ns
2t
CSC
SR SS to SCK delay
2
— — 16 — ns
3t
ASC
SR SCK to SS delay
2
— — 16 — ns
4t
SDC
CC SCK duty cycle
2
— — 30 — ns
5t
A
CC Slave Access
Time
2, 3, 4
(SS
active to SOUT
driven)
3
All timing values for output signals in this table, are measured to 50% of the output voltage.
4
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
Very strong 25 pF — 50 ns
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6t
DIS
CC Slave SOUT
Disable Time
2, 3,
4
(SS inactive to
SOUT High-Z or
invalid)
Very strong 25 pF — 5 ns
Strong 50 pF — 5 ns
Medium 50 pF — 10 ns
7t
SUI
CC Data setup time
for inputs
2
— — 10 — ns
8t
HI
CC Data hold time for
inputs
2
— — 10 — ns
9t
SUO
CC SOUT Valid
Time
2, 3, 4
(after
SCK edge)
Very strong 25 pF — 30 ns
Strong 50 pF — 30 ns
Medium 50 pF — 50 ns
10 t
HO
CC SOUT Hold
Time
2, 3, 4
(after
SCK edge)
Very strong 25 pF 2.5 — ns
Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns