NXP Semiconductors MPC5777M - Page 102

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors102
8t
HI
CC SIN Hold Time
SIN hold time
from SCK
CPHA = 0
6
SCK drive strength
LVDS 0 pF differential –1 + (P
7
×t
SYS
3
)—ns
SIN hold time
from SCK
CPHA = 1
6
SCK drive strength
LVDS 0 pF differential –1 — ns
9t
SUO
CC SOUT data valid time (after SCK edge)
SOUT data valid
time from SCK
CPHA = 0
8
SOUT and SCK drive strength
LVDS 15 pF
to 25 pF
differential
—7.0+t
SYS
3
ns
SOUT data valid
time from SCK
CPHA = 1
8
SOUT and SCK drive strength
LVDS 15 pF
to 25 pF
differential
—7.0ns
10 t
HO
CC SOUT data hold time (after SCK edge)
SOUT data hold
time after SCK
CPHA = 0
8
SOUT and SCK drive strength
LVDS 15 pF
to 25 pF
differential
–7.5 + t
SYS
3
—ns
SOUT data hold
time after SCK
CPHA = 1
8
SOUT and SCK drive strength
LVDS 15 pF
to 25 pF
differential
–7.5 — ns
1
All timing values for output signals in this table are measured to 50% of the output voltage.
2
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
3
t
SYS
is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
t
SYS
= 10 ns).
4
M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
5
t
SDC
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
6
Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.
7
P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically
set to 1.
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
# Symbol Characteristic
Condition Value
1
Unit
Pad drive Load Min Max