NXP Semiconductors MPC5777M - Page 101

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 101
Figure 34. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.3 DSPI LVDS Master Mode – Modified Timing
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
# Symbol Characteristic
Condition Value
1
Unit
Pad drive Load Min Max
1t
SCK
CC SCK cycle time LVDS 15 pF
to 25 pF
differential
30.0 — ns
2t
CSC
CC PCS to SCK delay
(LVDS SCK)
PCS drive strength
Very strong 25 pF (N
2
×t
SYS
3
)–10 — ns
Strong 50 pF (N
2
×t
SYS
3
)–10 — ns
Medium 50 pF (N
2
×t
SYS
3
)–32 — ns
3t
ASC
CC After SCK delay
(LVDS SCK)
Very strong PCS = 0 pF
SCK = 25 pF
(M
4
×t
SYS
3
)–8 — ns
Strong PCS = 0 pF
SCK = 25 pF
(M
4
×t
SYS
3
)–8 — ns
Medium PCS = 0 pF
SCK = 25 pF
(M
4
×t
SYS
3
)–8 — ns
4t
SDC
CC SCK duty cycle
5
LVDS 15 pF
to 25 pF
differential
1
/
2
t
SCK
–2
1
/
2
t
SCK
+2 ns
7t
SUI
CC SIN setup time
SIN setup time to
SCK
CPHA = 0
6
SCK drive strength
LVDS 15 pF
to 25 pF
differential
23–(P
7
×t
SYS
3
)—ns
SIN setup time to
SCK
CPHA = 1
6
SCK drive strength
LVDS 15 pF
to 25 pF
differential
23 — ns
PCSx
PCSS
t
PCSC
t
PASC