NXP Semiconductors LPC55S0x - Clock Circuitry; 4.1 Introduction

• The route distance between the capacitors to the power plane should be as short as possible.
Figure 3. Bulk and decoupling capacitor connection
4 Clock circuitry
4.1 Introduction
The LPC55S1x/2x/6x has the following clock sources:
• Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided
down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to +/- 2% accuracy
over the entire voltage and temperature range.
• 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2% accuracy over the entire voltage and
temperature range.
• Internal low power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the entire voltage and temperature range.
• Crystal oscillator with an operating frequency of 16 MHz or 32 MHz. Option for external clock input (bypass mode) for
clock frequencies of up to 24 MHz.
• Crystal oscillator with 32.768 kHz operating frequency. Option for external clock input (bypass mode) for clock frequencies
of up to 100 kHz.
• PLL0 and PLL1 allow CPU operation up to the maximum CPU rate without the need for a high-frequency external clock.
PLL0 and PLL1 can run from the internal FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the
32.768 kHz RTC oscillator.
• Clock output function with divider to monitor internal clocks.
• Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal.
For external crystal oscillator and RTC oscillator, LPC55Sxx have capacitor bank feature. It means that the
stabilizing capacitors can be unsoldered on both 32 K and 16 MHz XTAL. We also suggest users to keep the two
stabilizing capacitors as DNP/Do Not Populate on PCB.
NOTE
NXP Semiconductors
Clock circuitry
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 6 / 24