Table 6. Power domains and decoupling capacitors (continued)
Power
domain
Description Voltage
Bulk/Bypass capacitor for domain
Decoupling
capacitor
per pin
CharacteristicsPackage
HTQFP64 VFBGA98 HLFP100
VBAT_DCD
C
Supply of DCDC output
— 22 uF + 100 nF + 47 pF X7R Ceramic
VBAT_PMU
Core supply. For
applications with DCDC
converter, VDD_PMU
and FB are tied at
PCB level.
VDD_PMU Core supply
VDDA Analog supply voltage 1.8 - 3.6 V 10 uF 10 uF 10 uF 0.1 uF X7R ceramic
VREFP ADC positive reference
0.985 -
VDDA
10 uF 10 uF 10 uF 0.1 uF X7R Ceramic
VREFN ADC
negative reference
VSS, VSSA and VREFN must be shorted to GND at package level.
USB0_VSS USB0 analog 3.3
V ground
GND
USB1_VSS USB1 analog 3.3
V ground
VSS Ground
VSS_DCDC Star
ground connections
VSS_PMU Star
ground connections
VSSA Analog ground
FB Feedback node
LX
DCDC power
stage output
3.2 Bulk and decoupling capacitors
The effectiveness of the bulk/bypass and the de-coupling capacitors depends on the optimum placement and connection type.
The bulk capacitors are used for a local power supply to the power pin, near the decoupling capacitors and as close as possible
to the assigned reference voltage pin. Decoupling capacitors make the current loop between supply, MCU and reference ground
as short as possible to reduce high frequency transients and noises. Therefore,
• All decoupling capacitors should be placed as close as possible to each of their respective power supply pin.
• The ground side of the decoupling capacitor should have a via to the pad which goes directly down to the internal ground
plane.
NXP Semiconductors
Power supply
Hardware Design Guidelines for LPC55(S)xx Microcontrollers, Rev. 0, 30 October 2020
Application Note 5 / 24
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