NXP Semiconductors LPC1768 - ARM Cortex-M3 User Guide: Instruction Set; Instruction Set Summary; Note

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User manual Rev. 3 — 20 December 2013 649 of 841
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Chapter 34: Appendix: Cortex-M3 user guide
34.2 ARM Cortex-M3 User Guide: Instruction Set
34.2.1 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 612 lists the
supported instructions.
Note
In Table 612
:
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 612. Cortex-M3 instructions
Mnemonic Operands Brief description Flags Page
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V Section 34.2.5.1
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V Section 34.2.5.1
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V Section 34.2.5.1
ADR Rd, label Load PC-relative address - Section 34.2.4.1
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C Section 34.2.5.2
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C Section 34.2.5.3
B label Branch - Section 34.2.9.1
BFC Rd, #lsb, #width Bit Field Clear - Section 34.2.8.1
BFI Rd, Rn, #lsb, #width Bit Field Insert - Section 34.2.8.1
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C Section 34.2.5.2
BKPT #imm Breakpoint - Section 34.2.10.1
BL label Branch with Link - Section 34.2.9.1
BLX Rm Branch indirect with Link - Section 34.2.9.1
BX Rm Branch indirect - Section 34.2.9.1
CBNZ Rn, label Compare and Branch if Non Zero - Section 34.2.9.2
CBZ Rn, label Compare and Branch if Zero - Section 34.2.9.2
CLREX - Clear Exclusive - Section 34.2.4.9
CLZ Rd, Rm Count leading zeros - Section 34.2.5.4
CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V Section 34.2.5.5
CMP, CMPS Rn, Op2 Compare N,Z,C,V Section 34.2.5.5
CPSID iflags Change Processor State, Disable Interrupts - Section 34.2.10.2
CPSIE iflags Change Processor State, Enable Interrupts - Section 34.2.10.2
DMB - Data Memory Barrier - Section 34.2.10.3
DSB - Data Synchronization Barrier - Section 34.2.10.4
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C Section 34.2.5.2