UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 95 of 841
NXP Semiconductors
UM10360
Chapter 7: LPC176x/5x Pin configuration
7.1.1 LPC176x/5x pin description
I/O pins on the LPC176x/5x are 5V tolerant and have input hysteresis unless indicated in
the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant.
In addition, when pins are selected to be A to D converter inputs, they are no longer 5V
tolerant and must be limited to the voltage at the ADC positive reference pin (
V
REFP
).
Row J
1 P0[28]/SCL0/
USB_SCL
2 P0[27]/SDA0/
USB_SDA
3 P0[29]/USB_D+ 4 P1[19]/MCOA0/
USB_PPWR
/
CAP1[1]
5 P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
6V
SS
7 P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
8 P0[1]/TD1/RXD3/SCL1
9 P2[13]/EINT3
/
I2STX_SDA
10 P2[10]/EINT0/NMI 11 - 12 -
Row K
1 P3[26]/STCLK/
MAT0[1]/PWM1[3]
2V
DD(3V3)
3V
SS
4 P1[20]/MCI0/
PWM1[2]/SCK0
5 P1[23]/MCI1/
PWM1[4]/MISO0
6P1[26]/MCOB1/
PWM1[6]/CAP0[0]
7 P1[27]/CLKOUT
/USB_OVRCR
/
CAP0[1]
8 P0[0]/RD1/TXD3/SDA1
9 P0[11]/RXD2/
SCL2/MAT3[1]
10 P2[12]/EINT2
/
I2STX_WS
11 - 12 -
Table 72. Pin allocation table TFBGA100 package …continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
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