NXP Semiconductors LPC1768 - GPIO Interrupt Enable for Port 2 Falling Edge (Io2 Intenf - 0 X4002 80 B4)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 135 of 841
NXP Semiconductors
UM10360
Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
[1] Not available on 80-pin package.
9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4)
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 2 pin.
[1] Not available on 80-pin package.
28 P0.28EF
[1]
Enable falling edge interrupt for P0.28. 0
29 P0.29EF Enable falling edge interrupt for P0.29. 0
30 P0.30EF Enable falling edge interrupt for P0.30. 0
31 - Reserved. NA
Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)
bit description …continued
Bit Symbol Value Description Reset
value
Table 117. GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) bit
description
Bit Symbol Value Description Reset
value
0 P2.0EF Enable falling edge interrupt for P2.0 0
0 Falling edge interrupt is disabled on P2.0.
1 Falling edge interrupt is enabled on P2.0.
1 P2.1EF Enable falling edge interrupt for P2.1. 0
2 P2.2EF Enable falling edge interrupt for P2.2. 0
3 P2.3EF Enable falling edge interrupt for P2.3. 0
4 P2.4EF Enable falling edge interrupt for P2.4. 0
5 P2.5EF Enable falling edge interrupt for P2.5. 0
6 P2.6EF Enable falling edge interrupt for P2.6. 0
7 P2.7EF Enable falling edge interrupt for P2.7. 0
8 P2.8EF Enable falling edge interrupt for P2.8. 0
9 P2.9EF Enable falling edge interrupt for P2.9. 0
10 P2.10EF Enable falling edge interrupt for P2.10. 0
11 P2.11EF
[1]
Enable falling edge interrupt for P2.11. 0
12 P2.12EF
[1]
Enable falling edge interrupt for P2.12. 0
13 P2.13EF
[1]
Enable falling edge interrupt for P2.13. 0
31:14 - Reserved. NA